FPGA-in-the-Loop Simulation Workflows
You must have HDL code to perform FIL simulation. There are two FIL workflows:
You have existing HDL code (FIL wizard).
The FIL wizard uses any synthesizable HDL code including code automatically generated from Simulink® models by HDL Coder™ software
You have MATLAB® code or a Simulink model and an HDL Coder license (HDL workflow advisor).
When you use FIL in the Workflow Advisor, HDL Coder uses the loaded design to create the HDL code.
For either workflow, the first three steps are the same:
For the next step, click the link for the workflow you are going to follow:
If you have existing HDL code, select block or System object™ generation using the FIL wizard:
If you need the HDL workflow advisor to generate HDL code, select block or System object generation using HDL workflow advisor:
To use the HDL Coder HDL workflow advisor for Simulink to generate a FIL interface, you must have an HDL Coder license.