Serial Link Design
The Serial Link Designer app provides a dedicated system-level design and analysis environment for multi-gigabit serial links. Capture your serial link designs graphically and experiment with different physical layout and equalization strategies to predict how design alternatives affect operating margins and the bit error rate (BER) of the link. Use network characterization to model the behavior of the unequalized analog network. This enables quick evaluation of the analog channel design for different trade-offs. Predict the end-to-end behavior of the link using SerDes equalization techniques and clock recovery models obtained by statistical and time-domain analysis. Determine the effect of aggressor signals on overall BER of the channel using crosstalk analysis.
Use the Serial Link Designer app to configure high speed serial links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE, network characterization, statistical and time domain simulations to analyze your custom serial links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your serial link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.
Configure Serial Link Projects
- Simulation Parameters Used in Serial Link Design
Set parameters to control SPICE simulation and statistical, time domain, and waveform analysis.
- Specify Corner Conditions in Serial Link Design
Specify process corners and etch corners to simulate in serial link project.
- Stimulus Patterns in Serial Link Design
Define stimulus patterns for time domain analysis in serial link project.
- Model Jitter and Noise While Designing Serial Link
Add TX clock jitter, RX clock jitter, RX clock recovery jitter, and noise.
- Clock Modes
Learn about different clock modes in AMI models.
- Pre-Layout Analysis of Serial Link
Learn the basics of pre-layout analysis.
- Customize Serial Link Project for Pre-Layout Analysis
Edit transmission line models, designators, S-parameters, and IBIS files to customize pre-layout analysis.
- Results of Pre-Layout Analysis in Serial Link
View, interpret, and debug the pre-layout analysis results.
- Channel Operating Margin (COM)
Definition and usage of COM in serial link design.
- Eye Measurement and Reporting
Measure and report eye diagram metrics.
- Run Parallel Simulations in Signal Integrity Toolbox
Reduce the time required to run a complete set of simulations by running the simulations in parallel with Parallel Computing Toolbox™.
Post-Layout Verification (Requires RF PCB Toolbox)
- Post-Layout Verification of Serial Link
Verify system-level SI and timing margins of PCB design databases.
- Stackup and Extraction Control in Serial Link Project
Edit stackups and control padstack models.
- Via and Stackup Management in Serial Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.