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Generate Tests for Model Block Component by Using Default Simulation

This example shows how to use Simulink Design Verifier to generate test cases for a Model block by using a default top model simulation.

This example contains Model block that acts as a controller. The top model is configured for plant-in-loop simulation. You can generate test cases for a controller by using the top model simulation.

Set Up the Default Plant-in-Loop Controller Simulation

The model contains a power window controller and a low-order plant model. sldvexPowerWindow/power_window_control_system/control is a Model block that references the model sldvexPowerWindowController, which implements the controller with a Stateflow chart.

open_system('sldvexPowerWindow');

This model contains a Signal Editor block at the top level. The simulation is set up as a plant-in-loop controller simulation.

Simulate the Top Model and Generate Test Cases for the Controller

1. In the Apps pane, open Design Verifier.

2. In the Analyze section, click the Remember Selection icon to unpin the current selection.

3. Select the Model block sldvexPowerWindow/power_window_control_system/control.

4. In the Design Verifier tab, expand Generate Test and click Simulate Top Model And Generate Tests.

View Test Generation Results

Design Verifier runs the default simulation to log inputs for the Model block sldvexPowerWindow/power_window_control_system/control. Then Design Verifier runs a test extension on logged inputs to generate additional test cases for the controller.

Clean Up

Close the model.

close_system('sldvexPowerWindow');