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Isolate Verification Logic with Observers

You can isolate the verification logic in a model by using Observer Reference blocks. The Observer Reference blocks serve as an ideal candidate when you want to keep the verification logic separate from your design model. When you use an Observer Reference (Simulink Test), you can make changes to the Observer model without changing the design model. Using Observer Reference blocks can help you specify properties or requirements early in the model design or across multiple model designs. The Observer Reference block also allows you to:

  • Model design requirements as properties and prove them using Simulink® Design Verifier™.

  • Establish baseline results based on the captured output and detect model regressions.

  • Generate test cases for functional design requirements using custom test objectives.

Double-click an Observer Reference block to open the Observer model. Observer Reference blocks can only be at the top level of a system model and do not have input ports. For more information, see Access Model Data Wirelessly by Using Observers (Simulink Test).

Replace a Verification Subsystem with an Observer Reference Block

When authoring custom verification objectives, the Observer Reference block can be used in place of the Verification Subsystem block. The Observer Reference block references a separate verification model called the Observer model that you use to verify your system model. Converting a Verification Subsystem block to an Observer Reference block can declutter a system model. To convert a Verification Subsystem block to an Observer Reference block, right-click the verification subsystem and select Observers > Move selected block to Observer > New Observer. This operation cannot be undone. This action adds an Observer Reference block to your system model and opens the Observer model. You must save the Observer model in a writable folder on the MATLAB® path.

Consider the case where the model sldvdemo_debounce_validprop contains the Verification Subsystem block Verify Output.

By converting the subsystem to an Observer Reference block, you remove the signals that connect subsystem to the system model while preserving the ability to test the integrity of the system.

The two signals, debounce and raw, are automatically mapped to two Observer Port blocks in the Observer model, sldvdemo_debounce_validprop_Observer1.

You can verify the properties of sldvdemo_debounce_validprop without making any changes to the design model.

Report on Observer Reference Blocks

If your model includes an Observer Reference block, the Simulink Design Verifier analysis report shows the property proving and test case generation information for the Observer Reference blocks in the Observer Model(s) subsection and design model information in the Design Model subsection. For more information, see Simulink Design Verifier Reports.


  • Simulink Design Verifier does not support:

    • Observer Reference blocks that observe complex signals, bus signals, or Stateflow data.

    • Observer models that include Model Referenced blocks.

    • Applying block replacement rules to Observer models

    • Observer model that runs at different base rate than the design model.

    • Tuning the parameters inside Observer model.

    • Debugging property violations inside an Observer model using Model Slicer.

    • Test generation for code generated by Embedded Coder® for models that contain Observer Reference blocks.

  • Simulink Design Verifier does not analyze logic inside Observer models for design error and dead logic detection analysis.

The Simulink Design Verifier analysis returns an error when:

  • You analyze standalone Observers.

  • You perform subsystem extraction on an Observer Reference block.

  • The Observer model uses variable-step solver settings.

See Also

| | (Simulink Test) | (Simulink Test)

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