Deep Learning

Integrate deep learning processors with video streaming designs

SoC Blockset™ Support Package for AMD FPGA and SoC Devices provides two fixed reference designs for integrating deep learning processors with your streaming video designs.

Integrate a DL processor with custom preprocessing logic.
Connect live HDMI video to custom preprocessing logic, a DL processor, and custom postprocessing code, and then return the modified HDMI video output from the board.

Both designs use AXI manager interfaces, DDR memory, and an AXI4-Stream data path. Use the IP core generation workflow to generate code and deploy your design to an SoC device.

Topics

Target Deep Learning Processor and Image Preprocessing to FPGA
Reference design for processing video with a deep learning processor, including preprocessing logic in the FPGA.
Deep Learning Processing of Live Video
Reference design for processing live HDMI video with a deep learning processor, including preprocessing logic in the FPGA and postprocessing operations in the ARM^® processor.

Featured Examples

Deploy and Verify YOLO v2 Vehicle Detector on FPGA

Deploy a you only look once (YOLO) v2 vehicle detector on FPGA and verify the end-to-end application using MATLAB.

(Vision HDL Toolbox)

Debug YOLO v2 Vehicle Detector on FPGA

Debug a vehicle detector design by viewing internal signals while the design is deployed on a board.

(Vision HDL Toolbox)

Integrate YOLO v2 Vehicle Detector System on SoC

Simulate a YOLO v2 vehicle detection algorithm that contains FPGA and ARM sections for deployment to an SoC device.

(Vision HDL Toolbox)

YOLO v2 Vehicle Detector with Live Camera Input on Zynq-Based Hardware

Deploy a YOLO v2 vehicle detection algorithm to the FPGA and ARM processor on an SoC device and process live HDMI video input.

(Vision HDL Toolbox)

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