AD9361 Rx

Connect hardware logic to AD9361-based Zynq receiver

Use of this block is not recommended. Use AD936x Receiver instead. For more information, see Extended Capabilities.

Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

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Libraries:
SoC Blockset Support Package for Xilinx Devices / MPSoC / ZCU102
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZC706
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZedBoard

Description

The AD9361 Rx block connects your hardware logic to the AD9361 receiver hardware. In simulation, this block returns data from a file or input port. This block does not connect to the radio hardware from simulation.

The block supports up to two channels to receive data.

Examples

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset™ to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

• Open Script

Transmit and Receive Tones Using AD9361 Dual-Channels

Design, simulate, and deploy dual-channel application system with AD9361 RF card using SoC Blockset™ on Xilinx^® Zynq^® UltraScale+™ MPSoC ZCU102 Evaluation Kit.

• Open Script

Limitations

• In the hardware setup, set Hardware Board to one of the supported Xilinx boards. You can find the supported boards in the Libraries list at the top of this page. Set Add-on Card to None.

• This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.

Ports

Input

rxDataIn — Receiver data

complex matrix

Receiver data to pass through the block in simulation, specified as a complex matrix. The number of columns in the matrix depends on the number of channels in use. Each column corresponds to a channel of complex data sent via one channel. In single-channel mode, the number of elements in a column must be even.

This port supports complex values with these data types:

• 16-bit signed integers — Complex values are the raw 16-bit I and Q samples. The 12-bit value from the ADC of the AD9361 RF chip is sign-extended to 16 bits.

• Single-precision floating point — Complex values are scaled to the range of [–1, 1]. The block derives this value from the sign-extended 16 bits received data.

• Double-precision floating point — Complex values are scaled to the range of [–1, 1]. The block derives this value from the sign-extended 16 bits received data.

Dependencies

To enable this port, set the Simulation output parameter to From input port.

Data Types: int16 | single | double
Complex Number Support: Yes

Output

rxDataOut — Receiver data

complex matrix

Receiver data, returned as a complex matrix. The number of columns in the matrix depends on the number of channels in use. Each column corresponds to a channel of complex data received on one channel. The Simulation output parameter defines the source of this data.

This port supports complex values with these data types:

• 16-bit signed integers — Complex values are the raw 16-bit I and Q samples from the board. The 12-bit value from the ADC of the AD9361 RF chip is sign-extended to 16 bits.

• Single-precision floating point — Complex values are scaled to the range of [–1, 1]. The block derives this value from the sign-extended 16 bits received data.

• Double-precision floating point — Complex values are scaled to the range of [–1, 1]. The block derives this value from the sign-extended 16 bits received data.

Data Types: int16 | single | double
Complex Number Support: Yes

Parameters

Enable channel 1 — Option to enable channel 1

on (default) | off

Select this parameter to enable the receive channel 1.

Enable channel 2 — Option to enable channel 2

off (default) | on

Select this parameter to enable the receive channel 2.

Simulation output — Simulation behavior

Zeros (default) | From recorded file | From input port

Simulation behavior, specified as one of these values:

• Zeros –– Return zero-valued data.

• From recorded file –– Return data from a file, using the Dataset name and Source name parameters.

• From input port –– Pass through data from the input port.

Dataset name — Name of recorded file

rf_data_adsb.tgz (default) | file path

Name of recorded file, specified as a file path on the host computer or browse and select the file on the host computer. This block supports only TGZ files created using the SoC Blockset data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Dependencies

To enable this parameter, set Simulation output to From recorded file.

Source name — Name of dataset

RF data Ch-1 (default) | character vector

Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Dependencies

To enable this parameter, set Simulation output to From recorded file.

Sample time — Sample time of the block

1 (default) | positive scalar

Sample time of the block, specified as a positive scalar.

Data Types: double

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2019a

R2024b: Not recommended

Use of this block is not recommended. Use AD936x Receiver instead. The new AD936x Receiver block includes the functionality from this block, but supports both SoC builder workflow and IP core generation workflow. For more information about SoC workflows, see SoC Generation Workflows.

R2024a: Dual channels support

The block now supports two receive channels. You can enable dual channels by selecting the Enable channel 1 and Enable channel 2 parameters from the block mask.