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Convert video stream to YCbCr 4:2:2 pixel stream

Add-On Required: This feature requires the SoC Blockset Support Package for Xilinx Devices add-on.

  • HDMI Rx block

SoC Blockset Support Package for Xilinx Devices / MPSoC / ZCU102
SoC Blockset Support Package for Xilinx Devices / MPSoC / ZCU106
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZC706
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZedBoard


The HDMI Rx block converts raw video data to a YCbCr 4:2:2 pixel stream format. It can return data in pixel stream mode for hardware algorithm design or in frame mode for faster simulation. When you include this block in your design, the SoC Builder tool generates all the IP blocks necessary to receive video data from the FMC-HDMI-CAM card attached to your hardware board. None of the block parameters affect hardware behavior. When simulating, specify a video file to stream.

You must have Computer Vision Toolbox™ to use this block.


  • In the hardware setup, select one of the supported Xilinx® boards. You can find the supported boards in the Libraries list at the top of this page. Set Add-on Card to None.

  • This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.



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Single YCbCr 4:2:2 pixel in pixel stream, specified as a scalar in concatenated YCbCr 4:2:2 format, where

  • bits [1:8] represent Y.

  • bits [9:16] represent Cb or Cr, interleaved in time.

Data Types: uint16

Control signals accompanying output pixel stream, returned as a pixelcontrol (Vision HDL Toolbox) bus. The bus contains five Boolean signals indicating the validity of a pixel and its location within a frame.

When the Output mode parameter is Frame, the block sets all five signals in the pixelcontrol bus to true to indicate when the output data is valid.

Data Types: bus


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Select the video frame size as one of these values:

  • 480p SDTV (720x480p)

  • 576p SDTV (720x576p)

  • 720p HDTV (1280x720p)

  • 1080p HDTV (1920x1080p)

  • 160x120p

  • 320x240p

  • 640x480p

  • 800x600p

  • 1024x768p

  • 1280x768p

  • 1280x1024p

  • 1360x768p

  • 1366x768p

  • 1400x1050p

  • 1600x1200p

  • 1680x1050p

  • 1920x1200p

Specify whether the output is streamed one pixel per clock cycle or one frame per clock. Pixel mode better represents the hardware algorithm and is recommended for FPGA deployment. Frame mode enables faster simulation.


Specify the full path to an input video file. For information on the supported file types, see From Multimedia File (Computer Vision Toolbox).

Example: 'handshake_left.avi'

Block sample time, in seconds, specified as a positive scalar. The default value corresponds to a frame rate of 60 fps.

Selecting this option enables a To Video Display (Computer Vision Toolbox) block to display the input frame during simulation.

Extended Capabilities

Version History

Introduced in R2019a

See Also