PLL (3ph)

Determine frequency and fundamental component of three-phase signal phase angle

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Libraries:
Simscape / Electrical / Specialized Power Systems / Control

Description

The PLL (3ph) block models a Phase Lock Loop (PLL) closed-loop control system, which tracks the frequency and phase of a sinusoidal three-phase signal by using an internal frequency oscillator. The control system adjusts the internal oscillator frequency to keep the phases difference to 0.

The figure shows the internal diagram of the PLL.

The three-phase input signal is converted to a dq0 rotating frame (Park transform) using the angular speed of an internal oscillator. The quadrature axis of the signal, proportional to the phase difference between the abc signal and the internal oscillator rotating frame, is filtered with a Mean (Variable Frequency) block. A Proportional-Integral-Derivative (PID) controller, with an optional automatic gain control (AGC), keeps the phase difference to 0 by acting on a controlled oscillator. The PID output, corresponding to the angular velocity, is filtered and converted to the frequency, in hertz, which is used by the mean value.

Characteristics

Sample Time	Specified in the Sample Time parameter. Continuous when Sample Time = 0.
Scalar Expansion	No
Dimensionalized	No
Zero-Crossing Detection	Yes

Examples

The power_PLL example shows the use of the PLL (3ph) and PLL blocks.

The PLL block is fed by a sinusoidal signal of 60 Hz, increasing to 61 Hz from 0.5 s to 1.5 s. Notice that the frequency reaches the new frequency in a short response time.

The PLL (3ph) block is fed by three-phase sinusoidal signals increasing from 60 Hz to 61 Hz between 0.5 and 1.5 seconds. The PLL (3ph) frequency reaches the new frequency faster than the PLL due to the additional phase information.

The model sample time is parameterized with the variable Ts (with a default value of 0). To discretize the PLL block, at the MATLAB^® command prompt, enter

Ts = 50e-6

Ports

Input

abc — Normalized three-phase signals

vector

Normalized three-phase signals, in pu.

Output

freq — Measured frequency

scalar

Measured frequency, in hertz.

wt — Angle synchronized on zero crossing of fundamental of phase A

scalar in the range [0, 2*pi]

Angle (rad) varying between 0 and 2*pi, synchronized on zero crossings of the fundamental (positive-sequence) of phase A.

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Minimum frequency (Hz) — Minimum expected frequency of input signal

45 (default) | positive scalar

Minimum expected frequency of the input signal. This parameter sets the buffer size of the Mean (Variable Frequency) block used inside the block to compute the mean value.

Initial inputs [ Phase (degrees), Frequency (Hz) ] — Initial phase and frequency of input signal

[0, 60] (default) | vector of two elements

Initial phase and frequency of the input signal.

Regulator gains [ Kp, Ki, Kd ] — Proportional, integral, and derivative gains of internal PID controller

[180, 3200, 1] (default) | vector of three elements

Proportional, integral, and derivative gains of the internal PID controller. Use the gains to tune the PLL response time, overshoot, and steady-state error performances.

Time constant for derivative action (s) — Time constant for first-order filter

1e-4 (default) | nonnegative scalar

Time constant for the first-order filter of the PID derivative block.

Maximum rate of change of frequency (Hz/s) — Maximum positive and negative slope of signal frequency

12 (default) | positive scalar

Maximum positive and negative slope of the signal frequency.

Filter cut-off frequency for frequency measurement (Hz) — Second-order lowpass filter cut-off frequency

25 (default) | scalar

Second-order lowpass filter cut-off frequency.

Sample time — Block sample time

0 (default) | nonnegative scalar

Sample time of the block, in seconds. Set to 0 to implement a continuous block.

Enable automatic gain control — Automatic gain control option

on (default) | off

When you select this parameter, the PLL block optimizes its performances by scaling the PID regulator signal according to the input signal magnitude. Select this option when the input signal is not normalized.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2013a