D Latch
Libraries:
Simscape /
Electrical /
Integrated Circuits /
Logic
Description
The D Latch block implements a behavioral model of a D-type
latch. The block stores a one-bit value, either 0
(low
)
or 1
(high
).
The block has two input ports that control the latch: the data pin D and the
enable pin E. When the logic level at E is 1
, the
block transfers the data to the output pin Q. When the logic level at
E is 0
, the block holds the output in its previous state.
This truth table summarizes the logic levels at the inputs and output. The subscript
n
represents the value at the current time step and
n-1
represents the value at the previous time step. The logic level at
the inverted output pin !Q is the inverse of the logic level at
Q.
E_{n} | D_{n} | Q_{n} |
---|---|---|
0 | 0 | Q_{n-1} |
0 | 1 | Q_{n-1} |
1 | 0 | 0 |
1 | 1 | 1 |
To specify the logic level at Q at the start of the simulation, in the
Initial Targets section, set the value of the Output
logic parameter to 0
or 1
.
The block uses this value as the initial logic level at Q only if the initial
logic level at E is 0
. In this situation, the block
normally holds the output in its previous state. For more information about initial targets,
see Set Priority and Initial Target for Block Variables.
The gate inputs have an infinite resistance and a finite or zero capacitance.
If the gate voltage is greater than the threshold voltage, then the block takes the logic
level at the input as 1
. Otherwise, the block takes the logic level at the
input as 0
. The block calculates the threshold voltage as the average of
the Low level input voltage and the High level input
voltage parameter values.
The gate output depends on the Output current-voltage relationship
parameter. Set this parameter to Linear
for faster simulation and
Quadratic
for more accurate results. For most models, use the
Linear
option. You can use the
Quadratic
option to validate the results that you obtain using
the simpler linear model. For more information, see Selecting the Output Model for Logic Blocks.
If you set the Output current-voltage relationship parameter to
Linear
:
If the logic level at the Q port is
0
, the output voltage is equal to the Low level output voltage parameter value.If the logic level at the Q port is
1
, the output voltage is equal to the High level output voltage parameter value.The resistor-capacitor time constant of the gate output capacitor is equal to the Propagation delay parameter value.
If you set the Output current-voltage relationship parameter to
Quadratic
:
The output voltage is a function of the output current. For zero-load current:
If the logic level at the Q port is
0
, the output voltage is zero.If the logic level at the Q port is
1
, the output voltage is equal to the Supply voltage parameter value.
The gate input demand lags to approximate the Propagation delay parameter value.
For more information, see Quadratic Model Output and Parameters.
Plot Input and Output Waveforms
You can plot the input and output waveforms of the D Latch block without building a complete model. Use the plots to explore the impact of your parameter choices on device characteristics. If you parameterize the block from a datasheet, you can compare your plots to the datasheet to check that you parameterized the block correctly. If you have a complete working model but do not know which manufactured part to use, you can compare your plots to datasheets to help you decide.
To plot the basic characteristics, right-click the block and select Electrical > Basic characteristics from the context menu.
Note
The plots you create using the Basic characteristics option do not show the effect of the Propagation delay parameter on the output voltage of logic blocks.
Assumptions and Limitations
To improve simulation speed, the block does not model all the internal metal-oxide-semiconductor field-effect transistor (MOSFET) devices in the gate individually. The block therefore does not accurately model the response of the gate to input noise and input voltages that are close to the threshold voltage.
If you are modeling a circuit that has a feedback path around a set of logic gates, you must set the Propagation delay parameter to a nonzero value on one or more of the gates.
Ports
Conserving
Parameters
Extended Capabilities
Version History
Introduced in R2024a
See Also
D Flip-Flop | S-R Latch | Schmitt Trigger | CMOS AND | CMOS Buffer | CMOS NAND | CMOS NOR | CMOS NOT | CMOS OR | CMOS XOR