Connect hardware logic to AD9361-based Zynq transmitter
SoC Blockset Support Package for Xilinx Devices / SDR / AD9361
The AD9361 Tx block connects your hardware logic to the AD9361 transmitter hardware. In simulation, this block returns data to a file or output port. It does not connect to the radio hardware from simulation.
txDataIn — Transmit data
Transmit data, specified as scalar.
txValid — Validity of transmit data
Validity of the transmit data, specified as a Boolean scalar. When
1, the block captures the input
data from the txDataIn port. When txValid is
0, the block considers the input data as invalid and does not
txDataOut — Transmit data
Transmit data passed through the block, returned as a scalar.
To enable this port, set the Send simulation input to
Send simulation input to — Simulation behavior
Data file (default) |
Output port |
Simulation behavior, specified as one of these values:
Data file–– Export valid data from the txDataIn port to a file, using the Dataset name and Source name parameters.
Output port–– Pass through data from input port.
Terminator–– Connect the txValidIn port to a terminator inside the block.
Dataset name — Name of recorded file
rf_tx_data.tgz (default) | file path
Name of recorded file, specified as a file path on the host PC or browse and select the file on the host PC. This block supports only TGZ files created using the SoC Blockset™ data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.
To enable this parameter, set the Input source parameter to
Source name — Name of dataset
RF data Ch-1 (default) | character vector
Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.
HDL Code Generation
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Introduced in R2019a