AD9361 Tx

Connect hardware logic to AD9361-based Zynq transmitter

Since R2019a

• 

Libraries:
SoC Blockset Support Package for Xilinx Devices / SDR / AD9361

Description

The AD9361 Tx block connects your hardware logic to the AD9361 transmitter hardware. In simulation, this block returns data to a file or output port. It does not connect to the radio hardware from simulation.

Examples

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Ports

Input

txDataIn — Transmit data

scalar

Transmit data, specified as scalar.

Data Types: uint32

txValid — Validity of transmit data

Boolean scalar

Validity of the transmit data, specified as a Boolean scalar. When txValid is 1, the block captures the input data from the txDataIn port. When txValid is 0, the block considers the input data as invalid and does not capture it.

Output

txDataOut — Transmit data

scalar

Transmit data passed through the block, returned as a scalar.

Dependencies

To enable this port, set the Send simulation input to parameter to Output port.

Parameters

Send simulation input to — Simulation behavior

Data file (default) | Output port | Terminator

Simulation behavior, specified as one of these values:

• Data file –– Export valid data from the txDataIn port to a file, using the Dataset name and Source name parameters.

• Output port –– Pass through data from input port.

• Terminator –– Connect the txValidIn port to a terminator inside the block.

Dataset name — Name of recorded file

rf_tx_data.tgz (default) | file path

Name of recorded file, specified as a file path on the host PC or browse and select the file on the host PC. This block supports only TGZ files created using the SoC Blockset™ data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Dependencies

To enable this parameter, set the Input source parameter to From file.

Source name — Name of dataset

RF data Ch-1 (default) | character vector

Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Extended Capabilities

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2019a