Analog-to-digital converter (ADC)
C2000™ Microcontroller Blockset C281x
The C281x ADC block configures the C281x ADC to perform analog-to-digital conversion of signals connected to the selected ADC input pins. The ADC block outputs digital values representing the analog input signal and stores the converted values in the result register of your digital signal processor. You use this block to capture and digitize analog signals from external sources such as signal generators, frequency generators, or audio devices.
Data — ADC data
The output of the C281x ADC is a vector of
values. The output values are in the range 0 to 4095 because the C281x ADC is 12-bit
Module — Select module to use
A (default) |
A and B
Specify which DSP module to use:
A— Displays the ADC channels in module A (ADCINA0 through ADCINA7).
B— Displays the ADC channels in module B (ADCINB0 through ADCINB7).
A and B— Displays the ADC channels in both modules A and B (ADCINA0 through ADCINA7 and ADCINB0 through ADCINB7)
Then, use the check boxes to select the desired ADC channels.
Conversion mode — Select conversion type
Sequential (default) |
Type of sampling to use for the signals:
Sequential— Samples the selected channels sequentially
Simultaneous— Samples the corresponding channels of modules A and B at the same time
Start of conversion — Select start of conversion
Software (default) |
Specify the type of signal that triggers the conversion:
Software— Signal from software
EVA— Signal from Event Manager A (only for Module A)
EVB— Signal from Event Manager B (only for Module B)
External— Signal from external hardware
Sample time — Interval at which block reads data
Time in seconds between consecutive sets of samples that are converted for the
selected ADC channel(s). This is the rate at which values are read from the result
registers. To execute this block asynchronously, set Sample
-1, check the Post
interrupt at the end of conversion box.
To set different sample times for different groups of ADC channels, you must add separate C281x ADC blocks to your model and set the desired sample times for each block.
Data type — Select the output data type
uint16 (default) |
Date type of the output data.
Post interrupt at end of conversion — Enable to post an asynchronous interrupt
Off (default) |
Enable this check box to post an asynchronous interrupt at the end of each conversion. The interrupt is posted at the end of conversion.
Number of conversions — Select number of ADC channels for conversion
1 (default) |
Number of ADC channels to use for analog-to-digital conversions.
Conversions no. # — Select ADC channel for each conversion number
1 (default) |
Specific ADC channel to associate with each conversion number.
In oversampling mode, a signal at a given ADC channel can be sampled multiple times during a single conversion sequence. To oversample, specify the same channel for more than one conversion. Converted samples are output as a single vector.
Use multiple output ports — Enable to output multiple ports
off (default) |
If more than one ADC channel is used for conversion, you can use separate ports for each output and show the output ports on the block. If you use more than one channel and do not use multiple output ports, the data is output in a single vector.
The C281x ADC trigger mode depends on the internal setting of the source start-of-conversion (SOC) signal. In unsynchronized mode the ADC is usually triggered by software at the sample time intervals specified in the ADC block. For more information on configuring the specific parameters for this mode, see Configuring Acquisition Window Width for ADC Blocks.
In synchronized mode, the Event (EV) Manager associated with the same module as the ADC triggers the ADC. In this case, the ADC is synchronized with the pulse width modulator (PWM) waveforms generated by the same EV unit via the ADC Start Event signal setting. The ADC Start Event is set in the C281x PWM block. See that block for information on the settings.
The ADC cannot be synchronized with the PWM if the ADC is in cascaded mode.
The C281x ADC block supports ADC operation in dual and cascaded modes. In dual mode,
A or module
B can be
used for the ADC block, and two ADC blocks are allowed in the model. In cascaded mode,
A and module
B are used
for a single ADC block.
Introduced in R2016b