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Run Multiprocessor Models in External Mode

In multiprocessor external mode simulation, each processor reference model can be deployed run simultaneously on the processors contained in the SoC or microcontroller. While model run on the separate processors, you can interact with each model to observe signals, tune model parameters, and evaluate the overall behavior of the multiprocessor system when running on the hardware. This section describes the typical workflow configuration used to setup an external mode simulation onto a supported multiprocessor hardware board, such as the TI Delfino F2837xD.

Note

Hardware boards supporting multiprocessor deployment can be found in the C2000™ Microcontroller Blockset.

Process to Run Multiprocessor Model

  1. Create or open a multiprocessor SoC model and configure the model for a supported hardware board, such as the TI Delfino F2837xD. This figure shows an example of a minimal multiprocessor model. For more information on creating and configuring a multiprocessor model, see Multiprocessor Execution (SoC Blockset).

    Minimal two processor model

  2. Connect each CPU in the hardware board to your host computer. In the TI Delfino F2837xD, CPU1 can be connected using the SCIA native port which connects to the USB port on the TI Delfino F28379D Launch Pad hardware board. CPU2 can be connected to the host computer using an external FTDI, a serial to USB converter, connect to the SCIB native port on the hardware board. Both the SCIA and SCIB ports are now exposed as the COM ports on the host computer. Different hardware boards will require their own connection setup to expose their own connection ports, one for each processor in your system.

    Note

    The SCIB ports are mapped to the pins on the hardware boards as follows:

    • TI Delfino F28379D LaunchPad – Rx GPIO19 & Tx GPIO18b

    • TI Delfino F2837xD – Rx GPIO11 & Tx GPIO9

  3. Open one of the processor reference model. In the Simulink® toolstrip, on the System on Chip tab, click Hardware Settings to open the Configuration Parameter window.

  4. On the Hardware Implementation > Target Hardware Resources > External Mode tab, set the Communication interface to serial(using xcp). Set the Serial port to match COM port previously defined for that processor. Set the Baudrate to the maximum supported by the hardware board or else data drop may be observed.

  5. Check the Hardware Implementation > Task profiling on processor > Show in SDI to enable Simulation Data Inspector logging. Close the Configuration Parameter window.

  6. In the Simulink toolstrip, on the System on Chip tab, click Configure, Build & Deploy to launch the SoC Builder. For more information on SoC Builder, see SoC Builder.

  7. In the SoC Builder tool, on the Select Build Action screen, select Build and load for external mode. Click Next.

  8. In the following screen, select the CPUs that will run the external mode models.

  9. Complete the remaining steps and on the Run Application screen, click Load and Run to launch the external mode models on the processors. The models automatically start running in external mode.

  10. To stop the external mode execution, in the Simulink toolstrip, on the System on Chip tab, click Stop.

    Note

    You must stop all models. Stopping only one model while leaving others running can produce undefined behavior.

View External Mode Simulation Data

During and after running an external mode simulation on multiple processors, the tasks and signals can be viewed in the Simulation Data Inspector. Each processor records an independent run in the Simulation Data Inspector and contains all the tasks and signals that executed on that processor. Since the external mode is launched by the SoC Builder, all the runs for the separate processors share a common time, allowing comparison of the processor runs to each other to see the overall behavior of the software portion of your system on the SoC hardware.

Note

External mode, profiler, and data logging use the same communication channel. To prevent data drops and gaps, do not run external mode simulations with profiling or data logging enabled, and vice-versa.

See Also

| (SoC Blockset) |

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