Vision HDL Toolbox™ provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs. It provides a design framework that supports a diverse set of interface types, frame sizes, and frame rates. The image processing, video, and computer vision algorithms in the toolbox use an architecture appropriate for HDL implementations.
The toolbox algorithms are designed to generate readable, synthesizable code in VHDL® and Verilog® (with HDL Coder™). The generated HDL code is FPGA-proven for frame sizes up to 8k resolution and for high frame rate (HFR) video.
Toolbox capabilities are available as MATLAB® functions, System objects and Simulink® blocks.
This example shows how to design a hardware-targeted image filter using Vision HDL Toolbox™ blocks.
This example shows how to create a hardware-targeted design in Simulink® that implements the same behavior as a MATLAB® reference design.
This example shows how to design a hardware-targeted image filter using Vision HDL Toolbox™ objects.
This example shows how to accelerate a pixel-stream video processing algorithm in MATLAB® by using MATLAB Coder™.