HDL Code Generation and Verification


Simulink for HDL Code Generation and Verification 

Explore, implement and verify FPGA, SoC, or ASIC designs without having to write HDL code.

Design and explore at a high level, then generate and verify HDL directly from MATLAB® or Simulink® for FPGA, ASIC, or system-on-chip (SoC) prototype or production projects.

  • Generate optimized and readable VHDL® or Verilog® for any FPGA, ASIC, or SoC hardware
  • Connect system-level design with subsystem-level implementation
  • Build your hardware subsystem using high-quality hardware models for math, DSP, wireless communications, controls, and vision processing
  • Convert to fixed-point using automated guidance, or generate native floating-point operations for any target device
  • Deploy to and debug prototype hardware directly from Simulink and MATLAB
  • Reuse algorithm models and test cases 

"With Model-Based Design we can verify our algorithms and system functionality earlier, adapt to specification changes faster, and evaluate more design alternatives than with our traditional design flow. Model-Based Design helps bridge the gap between algorithm experts and RTL engineers.”

Mamoru Kamiya, Renesas System Design

Using MATLAB and Simulink for HDL Code Generation and Verification

HDL Code Generation for Any Target

Use high-level synthesis techniques to compile hardware-ready MATLAB or Simulink to readable, traceable, and synthesizable VHDL or Verilog HDL code. This code is optimized and portable across any FPGA, ASIC, or SoC hardware. 

You can produce high-quality HDL code regardless of your hardware design experience. Working at a high level lets you rapidly explore hardware architecture tradeoffs to meet your goals and automatically generate the HDL code and interfaces.

Model-Based Design Collaboration

With Simulink, algorithm developers can collaborate with hardware, software, and analog design engineers. They can use the same models to design, explore tradeoffs, and verify the system architecture before beginning implementation.

Generating HDL code directly from these models lets you adapt to changes, and it maintains traceability between the VHDL or Verilog, the model, and the requirements. 

HDL-Ready Models and Examples

Build your design using high-level blocks that simulate hardware implementations of algorithms and generate high-quality HDL code. Blocks include math, trigonometry, digital signal processing, wireless communications, and video and image processing. You can use subsystem-level intellectual property for LTE wireless and vision processing

Fixed-Point Made Easy

Automatically convert your data types from floating-point to fixed-point for implementation. This lets you balance resource usage and accuracy.

If your design has calculations that require high precision or a high dynamic range, or if you want to generate a prototype before converting to fixed-point, you can generate synthesizable target-independent native floating-point HDL.

Automatic FPGA and SoC Prototyping

For popular FPGA and SoC prototyping platforms from Xilinx®, Intel®, Microsemi®, and Speedgoat, you can generate everything you need to program the device with the push of a button. The prototype can run as a standalone device, or it can connect to MATLAB or Simulink for stimulus and debugging. You can then re-use it for production implementation on any FPGA, ASIC, or SoC. And you can set up custom prototype boards for easy programming.

Reuse Models and Tests for Verification

Cosimulate your MATLAB or Simulink models and tests together with handwritten or generated HDL code running in a Mentor Graphics® or Cadence® simulator. Then export these models and tests as SystemVerilog DPI-C components for your UVM or custom verification environment.