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Generate CRC code bits and append them to input data

Since R2024a



codeword = crcGenerate(msg,crcCfg) generates CRC checksums for the input message based on the specified CRC configuration object. The function appends the CRC checksums to the input message. For more information, see Algorithms.


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Generate two message words of length 6.

x = logical([1 0 1 1 0 1 0 1 1 1 0 1]');

Encode the message words using a 3-bit CRC generator.

cfgObj = crcConfig(Polynomial='z^3 + 1',ChecksumsPerFrame=2);
codeword = crcGenerate(x,cfgObj);

Add one bit error to each codeword.

errorPattern = randerr(2,9,1).';
codewordWithError = xor(codeword,errorPattern(:));

Decode messages with and without errors. The crcDetect function reports no errors in the transmitted message words for codeword and reports errors in both transmitted message words for codewordWithError.

[tx,err] = crcDetect(codeword,cfgObj);
[tx1,err1] = crcDetect(codewordWithError,cfgObj);

Apply the CRC-16-CCITT generator as described in Section of ITU-T Recommendation X-25 [1] by using the input data and expected frame check sequence (FCS) from Example 2 in Appendix I, I.1, where address = B and F = 1.

Create an unnumbered acknowledgement (UA) response frame.

Address = [1 0 0 0 0 0 0 0];
UA = [1 1 0 0 1 1 1 0];
input = [Address UA]';
expectedChecksum = [1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0]'; % Expected FCS
checksumLength = 16;

crcCfg = crcConfig( ...
    Polynomial='X^16 + X^12 + X^5 + 1', ...
    InitialConditions=1, ...
    DirectMethod=true, ...
crcSeq = crcGenerate(input,crcCfg);
checkSum =  crcSeq(end-checksumLength+1:end);

Compare calculated checksum with the expected checksum.

ans = logical


[1] ITU Telecommunication Standardization Sector. Series X: Data Networks and Open System Communication. Public Data Networks – Interfaces, 1997.

Generate a CRC-8 checksum for the example shown in 802.11™-2016[1], Section, and compare the result with the expected CRC.

Create a CRC configuration object that aligns with the CRC calculation in 802.11-2016. Set the generator polynomial to z8+z2+z+1. Set the initial conditions to 1. Set the algorithm to use the direct method. Set final XOR to 1.

crc8 = crcConfig(Polynomial=[8 2 1 0], ...
    InitialConditions=1, ...
    DirectMethod=true, ...
crc8 = 
  crcConfig with properties:

           Polynomial: [8 2 1 0]
    InitialConditions: 1
         DirectMethod: 1
    ReflectInputBytes: 0
     ReflectChecksums: 0
             FinalXOR: 1
    ChecksumsPerFrame: 1

Process one input frame according to the example from the 802.11-2016 standard in Section In the example, the input bit stream {m0, … m22} is {1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1} and the expected CRC checksum {c7, … c0} is {0 0 0 1 1 1 0 0}.

x = [1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1]';
expectedChecksum = [0 0 0 1 1 1 0 0]';
checksumLength = length(expectedChecksum);

Compare the generated CRC checksum to the expected checksum.

codeword = crcGenerate(x,crc8);
checksum = codeword(end-checksumLength+1:end);
ans = logical


[1] IEEE® 802.11™-2016. IEEE Standard for Information Technology — Local and Metropolitan Area Networks — Specific Requirements — Part 11: Wireless LAN MAC and PHY Specifications.

Input Arguments

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Input message, specified as binary values in a column vector or matrix.

Data Types: double | int8 | logical

CRC configuration, specified as a crcConfig object.

Data Types: crcConfig object

Output Arguments

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Output codeword, returned as binary values in a column vector or matrix with the same data type and number of columns as input msg. The output codeword contains the input msg with the generated checksums appended. When you input msg as a matrix, the appended checksums are computed for each column independently.

The length of the output frame is N + C × P bits, where N is the column length of the input msg, C is the number of checksums per frame (crcCfg.ChecksumsPerFrame), and P is the degree of the generator polynomial (crcCfg.Polynomial).


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CRC Generator Operation

The CRC generator appends CRC checksums to the input frame according to the specified generator polynomial and number of checksums per frame.

For a specific initial state of the internal shift register and k checksums per input frame:

  1. The input signal is divided into k subframes of equal size.

  2. Each of the k subframes are prefixed with the initial states vector.

  3. The CRC algorithm is applied to each subframe.

  4. The resulting checksums are appended to the end of each subframe.

  5. The subframes are concatenated and output as a column vector.

For the scenario shown here, a 10-bit frame is input, a z3 + z2 + 1 generator polynomial computes the CRC checksum, the initial state is 0, and the number of checksums per frame is 2.

CRC generator operation

The input frame is divided into two subframes of size 5, and checksums of size 3 are computed and appended to each subframe. The initial states are not shown because an initial state of [0] does not affect the output of the CRC algorithm. The output transmitted codeword frame has the size 5 + 3 + 5 + 3 = 16 bits.

Direct and Indirect CRC Algorithm

The crcGenerate function supports generation of CRC checksum by using the indirect or direct CRC algorithm. Subframe codewords are concatenated to output one frame. For matrix input signals, each column of input data is processed independently.

Indirect CRC Algorithm

The indirect CRC algorithm accepts a binary data vector, corresponding to a polynomial M, and appends a checksum of r bits, corresponding to a polynomial C. The concatenation of the input vector and the checksum then corresponds to the polynomial T = M×xr + C, since multiplying by xr corresponds to shifting the input vector r bits to the left. The algorithm chooses the checksum C so that T is divisible by a predefined polynomial P of degree r, called the generator polynomial.

The algorithm divides T by P, and sets the checksum equal to the binary vector corresponding to the remainder. That is, if T = Q×P + R, where R is a polynomial of degree less than r, the checksum is the binary vector corresponding to R. If necessary, the algorithm prepends zeros to the checksum so that it has length r.

The CRC generation feature, which implements the transmission phase of the CRC algorithm, does the following:

  1. Left shifts the input data vector by r bits and divides the corresponding polynomial by P.

  2. Sets the checksum equal to the binary vector of length r, corresponding to the remainder from step 1.

  3. Appends the checksum to the input data vector. The result is the output vector.

The CRC detection feature computes the checksum for its entire input vector, as described above.

The CRC algorithm uses binary vectors to represent binary polynomials, in descending order of powers. For example, the vector [1 1 0 1] represents the polynomial x3 + x2 + 1.

Block diagram for indirect CRC algorithm

Bits enter the linear feedback shift register (LFSR) from the lowest index bit to the highest index bit. The sequence of input message bits represents the coefficients of a message polynomial in order of decreasing powers. The message vector is augmented with r zeros to flush out the LFSR, where r is the degree of the generator polynomial. If the output from the leftmost register stage d(1) is a 1, then the bits in the shift register are XORed with the coefficients of the generator polynomial. When the augmented message sequence is completely sent through the LFSR, the register contains the checksum [d(1) d(2) . . . d(r)]. This is an implementation of binary long division, in which the message sequence is the divisor (numerator) and the polynomial is the dividend (denominator). The CRC checksum is the remainder of the division operation.

Direct CRC Algorithm

This block diagram shows the direct CRC algorithm.

Block diagram for the direct CRC algorithm

Where Message Block Input is m0,m1,...,mk1 and Code Word Output is


The initial step of the direct CRC encoding occurs with the three switches in position X. The algorithm feeds k message bits to the encoder. These bits are the first k bits of the code word output. Simultaneously, the algorithm sends k bits to the linear feedback shift register (LFSR). When the system completely feeds the kth message bit to the LFSR, the switches move to position Y. Here, the LFSR contains the mathematical remainder from the polynomial division. These bits are shifted out of the LFSR and they are the remaining bits (checksum) of the code word output.


[1] Sklar, Bernard. Digital Communications: Fundamentals and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1988.

[2] Wicker, Stephen B., Error Control Systems for Digital Communication and Storage. Upper Saddle River, NJ, Prentice Hall, 1995.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

Version History

Introduced in R2024a