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Multicore Architecture of Infineon AURIX

Design, simulate and generate code for multicore models of Infineon® AURIX™ TC3x microcontrollers

Microcontrollers in the Infineon AURIX TC3x family might contain up to six TriCore® processing units (TriCore 0 to TriCore 5). TriCore 0 is the principal processing unit that handles system initialization, boot processes, and critical control tasks in the AURIX microcontrollers. These processing units can run independently or collaboratively. You can assign different applications to individual processing units. To support modular and concurrent design in Simulink®, you can distribute components of a complex application across multiple processing units.

Embedded Coder® Support Package for Infineon AURIX TC3x Microcontrollers helps you to design multicore and single-core application models. The figure shows recommended modeling scenarios using different processing units of the Infineon AURIX TC4x microcontrollers. The figure shows the recommended modeling scenarios using different processing units (PU) of Infineon AURIX TC3x microcontrollers.

  • Monolithic models — A single or stand-alone Simulink model that generates one integrated application, which Simulink executes on a single processing unit.

  • SoC-based multicore models — A unified system-on-chip (SoC) architecture that generates one or more integrated applications for the participating processing units. The SoC models consist of a top-level model and two or more unique reference models. The top-level model represents an entire embedded system with application algorithms or models running on the reference models.

Infineon specific modeling scenarios for TC3x microcontrollers

Blocks

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ADC InterfaceConvert analog signal on ADC input pin to digital signal
PWM InterfaceSimulate pulse width modulation (PWM) output from hardware
Digital IO InterfaceSimulate digital input and output pins on processor (Since R2021b)
Interprocess Data ReadReceive messages from another processor using interprocess communication channel
Interprocess Data WriteSend messages to another processor using interprocessor data write
Interprocess Data ChannelModel interprocessor data channel between two processors
Task ManagerCreate and manage task executions in Simulink model
Event SourceSimulate and playback recorded task events

Tools

SoC BuilderBuild, load, and execute multicore application models on Infineon AURIX TC4x hardware boards (Since R2024b)
Hardware MappingMap tasks and peripherals in a model to hardware board configurations (Since R2022b)

Topics

Code Generation

Featured Examples