Complex PartialSystolic QR Decomposition
QR decomposition for complexvalued matrices
 Library:
FixedPoint Designer HDL Support / Matrices and Linear Algebra / Matrix Factorizations
Description
The Complex PartialSystolic QR Decomposition block uses QR decomposition to compute R and C = Q'B, where QR = A, and A and B are complexvalued matrices. The leastsquares solution to Ax = B is x = R\C. R is an upper triangular matrix and Q is an orthogonal matrix. To compute C = Q', set B to be the identity matrix.
When Regularization parameter is nonzero, the
Complex PartialSystolic QR Decomposition block transforms $$\left[\begin{array}{c}\lambda {I}_{n}\\ A\end{array}\right]$$ inplace to $$R=Q\text{'}\left[\begin{array}{c}\lambda {I}_{n}\\ A\end{array}\right]$$ and $$\left[\begin{array}{c}{0}_{n,p}\\ B\end{array}\right]$$ inplace to $$C=Q\text{'}\left[\begin{array}{c}{0}_{n,p}\\ B\end{array}\right]$$ where λ is the regularization parameter, QR is the
economy size QR decomposition of $$\left[\begin{array}{c}\lambda {I}_{n}\\ A\end{array}\right]$$, A is an mbyn
matrix, p is the number of columns in B,
I_{n} =
eye(n)
, and
0_{n,p} =
zeros(n,p)
.
Ports
Input
A(i,:)
— Rows of matrix A
vector
Rows of matrix A, specified as a vector. A is an mbyn matrix where m ≥ 2 and n ≥ 2. If B is single or double, A must be the same data type as B. If A is a fixedpoint data type, A must be signed, use binarypoint scaling, and have the same word length as B. Slopebias representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
Complex Number Support: Yes
B(i,:)
— Rows of matrix B
vector
Rows of matrix B, specified as a vector. B is an mbyp matrix where m ≥ 2. If A is single or double, B must be the same data type as A. If B is a fixedpoint data type, B must be signed, use binarypoint scaling, and have the same word length as A. Slopebias representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
Complex Number Support: Yes
validIn
— Whether inputs are valid
Boolean
scalar
Whether inputs are valid, specified as a Boolean scalar. This control signal
indicates when the data from the A(i,:)
and
B(i,:)
input ports are valid. When this value is 1
(true
) and the value at ready
is 1
(true
), the block captures the values on the
A(i,:)
and B(i,:)
input ports. When this
value is 0 (false
), the block ignores the input samples.
After sending a true
validIn
signal, there may be some delay before
ready
is set to false
. To ensure all data is
processed, you must wait until ready
is set to
false
before sending another true
validIn
signal.
Data Types: Boolean
restart
— Whether to clear internal states
Boolean
scalar
Whether to clear internal states, specified as a Boolean scalar. When this value
is 1 (true
), the block stops the current calculation and clears all
internal states. When this value is 0 (false
), and the
validIn
value is 1 (true
), the block begins
a new subframe.
Data Types: Boolean
Output
R
— Matrix R
matrix
Economysize QR decomposition matrix R, returned as a matrix. R is an upper triangular matrix. R has the same data type as A.
Data Types: single
 double
 fixed point
C
— Matrix C=Q'B
matrix
Economysize QR decomposition matrix C=Q'B, returned as a matrix or vector. C has the same number of rows as R. C has the same data type as B.
Data Types: single
 double
 fixed point
validOut
— Whether output data is valid
Boolean
scalar
Whether the output data is valid, returned as a Boolean scalar. This control
signal indicates when the data at output ports R
and
C
is valid. When this value is 1 (true
), the
block has successfully computed the R and C
matrices. When this value is 0 (false
), the output data is not
valid.
Data Types: Boolean
ready
— Whether block is ready
Boolean
scalar
Whether the block is ready, returned as a Boolean scalar. This control signal
indicates when the block is ready for new input data. When this value is 1
(true
), and the validIn
value is 1
(true
), the block accepts input data in the next time step. When
this value is 0 (false
), the block ignores input data in the next
time step.
After sending a true
validIn
signal, there may be some delay before
ready
is set to false
. To ensure all data is
processed, you must wait until ready
is set to
false
before sending another true
validIn
signal.
Data Types: Boolean
Parameters
Number of rows in matrices A and B
— Number of rows in input matrices A and B
4
(default)  positive integervalued scalar
The number of rows in input matrices A and B, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
m 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Number of columns in matrix A
— Number of columns in input matrix A
4
(default)  positive integervalued scalar
The number of columns in input matrix A, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
n 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Number of columns in matrix B
— Number of columns in input matrix B
1
(default)  positive integervalued scalar
The number of columns in input matrix B, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
p 
Type: character vector 
Values: positive integervalued scalar 
Default:
1 
Regularization parameter
— Regularization parameter
0 (default)  nonnegative scalar
Regularization parameter, specified as a nonnegative scalar. Small, positive values of the regularization parameter can improve the conditioning of the problem and reduce the variance of the estimates. While biased, the reduced variance of the estimate often results in a smaller mean squared error when compared to leastsquares estimates.
Programmatic Use
Block Parameter:
regularizationParameter 
Type: character vector 
Values: positive integervalued scalar 
Default:
0 
Algorithms
Choosing the Implementation Method
Partialsystolic implementations prioritize speed of computations over space constraints, while burst implementations prioritize space constraints at the expense of speed of the operations. The following table illustrates the tradeoffs between the implementations available for matrix decompositions and solving systems of linear equations.
Implementation  Ready  Latency  Area  Sample block or example 

Systolic  C  O(n)  O(mn^{2})  Implement HardwareEfficient QR Decomposition Using CORDIC in a Systolic Array 
PartialSystolic  C  O(m)  O(n^{2})  
PartialSystolic with Forgetting Factor  C  O(n)  O(n^{2})  FixedPoint HDLOptimized MinimumVariance DistortionlessResponse (MVDR) Beamformer 
Burst  O(n)  O(mn^{2})  O(n) 
Where C is a constant proportional to the word length of the data, m is the number of rows in matrix A, and n is the number of columns in matrix A.
Block Timing
The following table provides details on the timing for the QR decomposition blocks.
Block  validIn to ready (c cycles)  validIn to validOut (v cycles) 

Real PartialSystolic QR Decomposition  c = w + 8  v = c(m + n  1) 
Complex PartialSystolic QR Decomposition  c = 2w + 15  v = c(m + n  1) 
Real PartialSystolic Qless QR Decomposition  c = w + 8  v = c(m + n  1) 
Complex PartialSystolic Qless QR Decomposition  c = 2w + 15  v = c(m + n  1) 
Real PartialSystolic Qless QR Decomposition with Forgetting Factor  c = w + 8  v = c(2n  1) 
Complex PartialSystolic Qless QR Decomposition with Forgetting Factor  c = 2w + 15  v = c(2n  1) 
In the table, m represents the number of rows in matrix A, and n is the number of columns in matrix A. w represents the word length of A.
If the data type of A is fixed point, then w is the word length.
If the data type of A is double, then w is 53.
If the data type of A is single, then w is 24.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Slopebias representation is not supported for fixedpoint data types.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
General  

ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Supports fixedpoint data types only.
FixedPoint Conversion
Design and simulate fixedpoint systems using FixedPoint Designer™.
Version History
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