mpower, ^
Fixed-point matrix power (^)
Syntax
Description
Examples
Square a Matrix
Compute the power of a 2-dimensional square matrix for exponent values 0, 1, 2, and 3.
x = fi([0 1; 2 4], 1, 32); px0 = x^0
px0 = 1 0 0 1 DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 1 FractionLength: 0
px1 = x^1
px1 = 0 1 2 4 DataTypeMode: Fixed-point: binary point scaling Signedness: Signed WordLength: 32 FractionLength: 28
px2 = x^2
px2 = 2 4 8 18 DataTypeMode: Fixed-point: binary point scaling Signedness: Signed WordLength: 65 FractionLength: 56
px3 = x^3
px3 = 8 18 36 80 DataTypeMode: Fixed-point: binary point scaling Signedness: Signed WordLength: 98 FractionLength: 84
Input Arguments
A
— Base
scalar | matrix
Base, specified as a scalar or matrix.
Example: x = fi([0 1; 2 4],1,32);
Data Types: fi
Complex Number Support: Yes
k
— Exponent
positive real-valued integer
Exponent, specified as a real-valued integer.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fi
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.
Usage notes and limitations:
When the exponent
k
is a variable and the input is a scalar, theProductMode
property of the governingfimath
must beSpecifyPrecision
.When the exponent
k
is a variable and the input is not scalar, theSumMode
property of the governingfimath
must beSpecifyPrecision
.variable-size inputs are only supported when the
SumMode
property of the governingfimath
is set toSpecifyPrecision
orKeep LSB
.For variable-size signals, you may see different results between the generated code and MATLAB®.
In the generated code, the output for variable-size signals is computed using the
SumMode
property of the governingfimath
.In MATLAB, the output for variable-size signals is computed using the
SumMode
property of the governingfimath
when the first input,A
, is nonscalar. However, whenA
is a scalar, MATLAB computes the output using theProductMode
of the governingfimath
.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
Both inputs must be scalar, and the exponent input, k
, must be a
constant integer.
Version History
Introduced in R2010a
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