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reinterpretcast

Convert fixed-point or integer data types without changing underlying data

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Syntax

c = reinterpretcast(a,T)

Description

c = reinterpretcast(a,T) converts the input a to the data type specified by numerictype object T without changing the underlying data. The result is returned in fi object c.

The reinterpretcast function differs from the MATLAB® typecast and cast functions in that it only operates on fi objects and built-in integers, and it does not allow the word length of the input to change.

example

Examples

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Open Live Script

In this example, a is a signed fi object with a word length of 8 bits and a fraction length of 7 bits. The reinterpretcast function converts a into an unsigned fi object c with a word length of 8 bits and a fraction length of 0 bits. The real-world values of a and c are different, but their binary representations are the same.

a = fi([-1 pi/4],1,8,7)
a = 
   -1.0000    0.7891

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Signed
            WordLength: 8
        FractionLength: 7

T = numerictype(0,8,0);
c = reinterpretcast(a,T)
c = 
   128   101

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 8
        FractionLength: 0

To verify that the underlying data has not changed, compare the binary representations of a and c.

binary_a = bin(a)
binary_a = 
'10000000   01100101'

binary_c = bin(c)
binary_c = 
'10000000   01100101'

Input Arguments

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Input fixed-point or integer array, specified as a scalar, vector, matrix, or multidimensional array.

The word length of inputs a and T must be the same.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fi
Complex Number Support: Yes

New data type, specified as a numerictype object that fully specified a fixed-point data type.

The word length of inputs a and T must be the same.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced in R2008b

See Also

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