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hdlcoder.optimizeDesign

Automatic iterative HDL design optimization

Description

example

hdlcoder.optimizeDesign(model, optimizationCfg) automatically optimizes your generated HDL code based on the optimization configuration you specify.

example

hdlcoder.optimizeDesign(model, cpGuidanceFile) regenerates the optimized HDL code without rerunning the iterative optimization, by using data from a previous run of hdlcoder.optimizeDesign.

Examples

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Maximize the clock frequency for a model, sfir_fixed, by performing up to 10 optimization iterations.

Open the model and specify the DUT subsystem.

model = 'sfir_fixed';
dutSubsys = 'symmetric_fir';
open_system(model);
hdlset_param(model,'HDLSubsystem',[model,'/',dutSubsys]);

Set your synthesis tool and target device options.

hdlset_param(model,'SynthesisTool','Xilinx ISE', ...
                   'SynthesisToolChipFamily','Zynq', ...
                   'SynthesisToolDeviceName','xc7z030', ...
                   'SynthesisToolPackageName','fbg484', ...
                   'SynthesisToolSpeedValue','-3')

Enable HDL test bench generation.

hdlset_param(model,'GenerateHDLTestBench','on');

Save your model.

You must save your model if you want to regenerate code later without rerunning the iterative optimizations, or resume your run if it is interrupted. When you use hdlcoder.optimizeDesign to regenerate code or resume an interrupted run, HDL Coder™ checks the model checksum and generates an error if the model has changed.

Create an optimization configuration object, oc.

oc = hdlcoder.OptimizationConfig;

Set the iteration limit to 10.

oc.IterationLimit = 10;

Optimize the model.

hdlcoder.optimizeDesign(model,oc)
hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx ISE');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Zynq');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7z030');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'fbg484');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-3');

Iteration 0
Generate and synthesize HDL code ...
(CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 143.66 Iteration 1
Generate and synthesize HDL code ...
(CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 278.72 Iteration 2
Generate and synthesize HDL code ...
(CP ns) 10.25	(Constraint ns) 12.73	(Elapsed s) 427.22 Iteration 3
Generate and synthesize HDL code ...
(CP ns) 9.55	(Constraint ns) 9.73	(Elapsed s) 584.37 Iteration 4
Generate and synthesize HDL code ...
(CP ns) 9.55	(Constraint ns) 9.38	(Elapsed s) 741.04 Iteration 5
Generate and synthesize HDL code ...
Exiting because critical path cannot be further improved.
Summary report: summary.html
Achieved Critical Path (CP) Latency : 9.55 ns		Elapsed : 741.04 s
Iteration 0: (CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 143.66
Iteration 1: (CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 278.72
Iteration 2: (CP ns) 10.25	(Constraint ns) 12.73	(Elapsed s) 427.22
Iteration 3: (CP ns) 9.55	(Constraint ns) 9.73	(Elapsed s) 584.37
Iteration 4: (CP ns) 9.55	(Constraint ns) 9.38	(Elapsed s) 741.04
Final results are saved in
    /tmp/hdlsrc/sfir_fixed/hdlexpl/Final-07-Jan-2014-17-04-41
Validation model: gm_sfir_fixed_vnl

Then HDL Coder stops after five iterations because the fourth and fifth iterations had the same critical path, which indicates that the coder has found the minimum critical path. The design’s maximum clock frequency after optimization is 1 / 9.55 ns, or 104.71 MHz.

Optimize a model, sfir_fixed, to a specific clock frequency, 50 MHz, by performing up to 10 optimization iterations, and do not generate an HDL test bench.

Open the model and specify the DUT subsystem.

model = 'sfir_fixed';
dutSubsys = 'symmetric_fir';
open_system(model);
hdlset_param(model,'HDLSubsystem',[model,'/',dutSubsys]);

Set your synthesis tool and target device options.

hdlset_param(model,'SynthesisTool','Xilinx ISE', ...
                   'SynthesisToolChipFamily','Zynq', ...
                   'SynthesisToolDeviceName','xc7z030', ...
                   'SynthesisToolPackageName','fbg484', ...
                   'SynthesisToolSpeedValue','-3')

Disable HDL test bench generation.

hdlset_param(model,'GenerateHDLTestBench','off');

Save your model.

You must save your model if you want to regenerate code later without rerunning the iterative optimizations, or resume your run if it is interrupted. When you use hdlcoder.optimizeDesign to regenerate code or resume an interrupted run, HDL Coder checks the model checksum and generates an error if the model has changed.

Create an optimization configuration object, oc.

oc = hdlcoder.OptimizationConfig;

Configure the automatic iterative optimization to stop after it reaches a clock frequency of 50MHz, or 10 iterations, whichever comes first.

oc.ExplorationMode = ...
    hdlcoder.OptimizationConfig.ExplorationMode.TargetFrequency;
oc.TargetFrequency = 50;
oc.IterationLimit = 10; =  

Optimize the model.

hdlcoder.optimizeDesign(model,oc)
hdlset_param('sfir_fixed','GenerateHDLTestBench','off');
hdlset_param('sfir_fixed','HDLSubsystem','sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed','SynthesisTool','Xilinx ISE');
hdlset_param('sfir_fixed','SynthesisToolChipFamily','Zynq');
hdlset_param('sfir_fixed','SynthesisToolDeviceName','xc7z030');
hdlset_param('sfir_fixed','SynthesisToolPackageName','fbg484');
hdlset_param('sfir_fixed','SynthesisToolSpeedValue','-3');

Iteration 0
Generate and synthesize HDL code ...
(CP ns) 16.26	(Constraint ns) 20.00	(Elapsed s) 134.02 Iteration 1
Generate and synthesize HDL code ...
Exiting because constraint (20.00 ns) has been met (16.26 ns).
Summary report: summary.html
Achieved Critical Path (CP) Latency : 16.26 ns		Elapsed : 134.02 s
Iteration 0: (CP ns) 16.26	(Constraint ns) 20.00	(Elapsed s) 134.02
Final results are saved in
    /tmp/hdlsrc/sfir_fixed/hdlexpl/Final-07-Jan-2014-17-07-14
Validation model: gm_sfir_fixed_vnl

Then HDL Coder stops after one iteration because it has achieved the target clock frequency. The critical path is 16.26 ns, a clock frequency of 61.50 GHz.

Run additional optimization iterations for a model, sfir_fixed, using saved iteration data, because you terminated in the middle of a previous run.

Open the model and specify the DUT subsystem.

model = 'sfir_fixed';
dutSubsys = 'symmetric_fir';
open_system(model);
hdlset_param(model,'HDLSubsystem',[model,'/',dutSubsys]);

Set your synthesis tool and target device options to the same values as in the interrupted run.

hdlset_param(model,'SynthesisTool','Xilinx ISE', ...
                   'SynthesisToolChipFamily','Zynq', ...
                   'SynthesisToolDeviceName','xc7z030', ...
                   'SynthesisToolPackageName','fbg484', ...
                   'SynthesisToolSpeedValue','-3')

Enable HDL test bench generation.

hdlset_param(model,'GenerateHDLTestBench','on');

Create an optimization configuration object, oc.

oc = hdlcoder.OptimizationConfig;

Configure the automatic iterative optimization to run using data from the first iteration of a previous run.

oc.ResumptionPoint = 'Iter5-07-Jan-2014-17-04-29';

Optimize the model.

hdlcoder.optimizeDesign(model,oc)
hdlset_param('sfir_fixed','HDLSubsystem','sfir_fixed/symmetric_fir');
hdlset_param('sfir_fixed','SynthesisTool','Xilinx ISE');
hdlset_param('sfir_fixed','SynthesisToolChipFamily','Zynq');
hdlset_param('sfir_fixed','SynthesisToolDeviceName','xc7z030');
hdlset_param('sfir_fixed','SynthesisToolPackageName','fbg484');
hdlset_param('sfir_fixed','SynthesisToolSpeedValue','-3');

Try to resume from resumption point: Iter5-07-Jan-2014-17-04-29
Iteration 5
Generate and synthesize HDL code ...
Exiting because critical path cannot be further improved.
Summary report: summary.html
Achieved Critical Path (CP) Latency : 9.55 ns		Elapsed : 741.04 s
Iteration 0: (CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 143.66
Iteration 1: (CP ns) 16.26	(Constraint ns) 5.85	(Elapsed s) 278.72
Iteration 2: (CP ns) 10.25	(Constraint ns) 12.73	(Elapsed s) 427.22
Iteration 3: (CP ns) 9.55	(Constraint ns) 9.73	(Elapsed s) 584.37
Iteration 4: (CP ns) 9.55	(Constraint ns) 9.38	(Elapsed s) 741.04
Final results are saved in
    /tmp/hdlsrc/sfir_fixed/hdlexpl/Final-07-Jan-2014-17-07-30
Validation model: gm_sfir_fixed_vnl

Then coder stops after one additional iteration because it has achieved the target clock frequency. The critical path is 9.55 ns, or a clock frequency of 104.71 MHz.

Regenerate HDL code using the original model, sfir_fixed, and saved data from the final iteration of a previous optimization run.

Open the model and specify the DUT subsystem.

model = 'sfir_fixed';
dutSubsys = 'symmetric_fir';
open_system(model);
hdlset_param(model,'HDLSubsystem',[model,'/',dutSubsys]);

Set your synthesis tool and target device options to the same values as in the original run.

hdlset_param(model,'SynthesisTool','Xilinx ISE', ...
                   'SynthesisToolChipFamily','Zynq', ...
                   'SynthesisToolDeviceName','xc7z030', ...
                   'SynthesisToolPackageName','fbg484', ...
                   'SynthesisToolSpeedValue','-3')

Regenerate HDL code using saved optimization data from cpGuidance.mat.

hdlcoder.optimizeDesign(model, 
  'hdlsrc/sfir_fixed/hdlexpl/Final-19-Dec-2013-23-05-04/cpGuidance.mat')
Final results are saved in 
  /tmp/hdlsrc/sfir_fixed/hdlexpl/Final-07-Jan-2014-17-16-52
Validation model: gm_sfir_fixed_vnl

Input Arguments

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Model name, specified as a character vector.

Example: 'sfir_fixed'

Optimization configuration, specified as an hdlcoder.OptimizationConfig object.

File that contains saved data from the final optimization iteration, including relative path, specified as a character vector. Use this file to regenerate optimized code without rerunning the iterative optimization.

The file name is cpGuidance.mat. You can find the file in the iteration folder name that starts with Final, which is a subfolder of hdlexpl.

Example: 'hdlexpl/Final-11-Dec-2013-23-17-10/cpGuidance.mat'

Introduced in R2014a