Automatic iterative optimization enables you to optimize your clock frequency without specifying individual optimization options, such as input or output pipelining, distributed pipelining, or loop unrolling.
There are two ways to use
hdlcoder.optimizeDesign to optimize
your clock frequency:
Best clock frequency: You specify the maximum number of iterations you want HDL Coder™ to perform, and the coder iterates to minimize the critical path in your design.
Target clock frequency: You specify a clock frequency target for your design and the maximum number of iterations you want HDL Coder to perform. The coder iterates until it meets your target clock frequency or reaches the maximum number of iterations.
HDL Coder can also determine that your target clock frequency is not achievable because your target clock period is less than the latency of the largest atomic combinational group of logic in your design.
You specify your clock frequency goal and the maximum number of iterations. HDL Coder performs the following steps for each iteration:
Analyzes the logic in your design.
Uses the synthesis tool to analyze the generated code, and obtains post-map timing analysis data.
Back annotates the design with the timing analysis data.
Inserts pipeline registers to break the critical path.
Saves iteration data in a new folder.
When HDL Coder has met your clock frequency goal or it has reached the maximum number of iterations, it saves the generated code and iteration data in a new folder and generates a report that describes the final critical path.
When HDL Coder exits the optimization loop, it saves the results of the final
iteration in a folder,
The final iteration folder contains:
The generated HDL code, in
A data file,
cpGuidance.mat, that you can use with
your original model to regenerate code without rerunning the iterative
The optimization report,
HDL Coder also saves
HDL Coder generates a report for the final optimization iteration and saves it
in the final iteration folder,
The final optimization report,
summary.html, contains the following:
Summary Section, with:
Final critical path latency.
Critical path latency and elapsed time for each iteration.
Diagnostic Section, with:
Reason for stopping at the final iteration.
Model or block settings that can reduce the accuracy of the critical path analysis.
If your model has these settings, remove them where
possible, and rerun
optimizations, such as distributed pipelining and
constrained output pipeline, change the placement of
pipeline registers after the coder analyzes the critical
Critical path description, which shows signals and components in both the original model and generated model that are part of the critical path.
You may see a message that says a signal or component on the critical path cannot be traced back to the original model. HDL Coder may not be able to map its internal representation of your design back to the original design. Each optimization iteration changes the internal representation, so the final representation can have a structure that is different from your original design.
Your synthesis tool must be Xilinx® ISE or Xilinx Vivado®, and your target device must be a Xilinx FPGA.
In the current release, automatic iterative optimization does not support Altera® hardware.
Running automatic iterative optimization can take a long time, depending
on the complexity of your design. To help mitigate the time cost,
hdlcoder.optimizeDesign can regenerate code from a
previous run, or resume from an interrupted run.
Automatic iterative optimization is available from the command line only.
HDL Coder uses post-map timing information, which the synthesis tool generates before performing place and route. Post-map timing information is less accurate than timing information the synthesis tool generates after place and route, but is faster to obtain.