addAXI4SlaveInterface

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add and define AXI4 slave interface

Syntax

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,Name,Value)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value)


Description

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr) adds and defines an AXI4 interface for an Altera^® reference design or an AXI4 or AXI4-Lite interface for a Xilinx^® ISE reference design.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado^® reference designs.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,Name,Value) adds and defines an AXI4 interface for an Altera reference design or an AXI4 or AXI4-Lite interface for a Xilinx ISE reference design, with additional options specified by one or more Name,Value arguments.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado reference designs, with additional options specified by one or more Name,Value arguments.

Input Arguments

ref_design_port — Reference design port name

'' (default) | character vector

Reference design port that is connected to the AXI4 or AXI4-Lite interface, specified as a character vector. For reference designs based on Intel^® Qsys™, when you want to connect multiple AXI Master IPs to the AXI4 or AXI4-Lite interface, specify each of the AXI Master instance names and the corresponding port names as a cell array of character vectors.

Example: 'axi_interconnect_0/M00_AXI', {'hps_0.h2f_axi_master','master_0.master'},...

base_addr — Base address

'' (default) | character vector

Base address for AXI4 or AXI4-Lite slave interface, specified as a character vector.

Example: '0x40010000'

master_addr_space — Master interface address space (Vivado only)

'' (default) | character vector

Address space of the master interface connected to this slave interface, specified as a character vector. For Vivado reference designs only. When you want to connect more than one AXI Master IP, specify each of the AXI Master instance names and the corresponding address spaces.

Example: 'processing_system7_0/Data', {'processing_system7_0/Data','hdlverifier_axi_master_0/axi4m'}

Name-Value Pair Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

InterfaceType — Interface type

{'AXI4-Lite','AXI4'} (default) | 'AXI4' | 'AXI4-Lite'

Type of interface connection, specified as a character vector or a cell array of character vectors.

Example: 'InterfaceType','AXI4-Lite' specifies an 'AXI4–Lite' interface type connection.

InterfaceID — Interface name

{'AXI4-Lite','AXI4'} (default) | character vector

Name of the interface, specified as a character vector. When you provide the InterfaceID, InterfaceType must be set to either 'AXI4' or 'AXI4–Lite'.

Example: 'InterfaceID','MyAXI4','InterfaceType','AXI4' specifies interface name as 'MyAXI4' and interface type as 'AXI4'.

IDWidth — Width of ID signals

positive integer

IDWidth is the width of all ID signals, such as AWID, WID, ARID, and RID, specified as a positive integer. The ID width only applies when you use the AXI4 interface and does not apply for the AXI4-Lite interface.

The ID width value is tool-specific, and may need to increase when the AXI4 slave interface on the DUT IP core is connected to multiple master interfaces. If you specify a value and enable the Insert AXI Manager parameter, HDL Coder™ increments the ID with value by one. if you do not specify the ID width, HDL Coder attempts to calculate the correct ID with based on the number of masters in the design.

Example: 'IDWidth','13'

HasProcessorConnection — Indicate AXI4 slave connection to processor

true (default) | false | logical data type

Indicate if the processor is one of the masters to the IP core AXI4 slave interface. To enable device tree generation for the IP core AXI4 slave interface, keep this value set to true.

Example: 'HasProcessorConnection','false'

DeviceTreeNodes — Reference to processor AXI4 master bus node in the device tree

" " (default) | string | character vector

Reference to the processor AXI4 master bus node in the device tree. Set this value to match the name of the corresponding bus node in the registered device tree. References to device tree nodes must start with "&". To reference a node by its label, specify "&" before the label, such as "&myLabel". To reference a node by its path, specify the path inside "&{" and "}", such as "&{/myNode/childNode}".

Example: 'DeviceTreeNodes','&fpga_axi'

Tips

• Before running this method, you must run the addClockInterface method.

• The addAXI4SlaveInterface method is optional. You can define your own custom reference design without the AXI4 slave interface.

• To connect the HDL IP core for your DUT to multiple AXI Master interfaces in the reference design, use the IDWidth property of this method. To learn more, see Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Slave Interface.

Version History

Introduced in R2015a