hdldispblkparams

Display HDL block parameters with nondefault values

Syntax

hdldispblkparams(path)

hdldispblkparams(path,"all")

Description

hdldispblkparams(path) displays, for the specified block or subsystem, the names and values of HDL parameters that have nondefault values.

hdldispblkparams(path,"all") displays, for the specified block or subsystem, the names and values of all HDL block parameters.

Examples

HDL Block Parameters and Values

This example displays all of the HDL block parameters and values for the subsystem symmetric_fir in the current model, sfir_fixed.

open_system("sfir_fixed")
hdldispblkparams("sfir_fixed/symmetric_fir","all")

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
HDL Block Parameters ('sfir_fixed/symmetric_fir')
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Implementation

	Architecture  : Module

Implementation Parameters

	AdaptivePipelining : inherit
	AXI4RegisterReadback : off
	AXI4SlaveIDWidth : 
	AXI4SlavePortToPipelineRegisterRatio : auto
	BalanceDelays : inherit
	ClockDomainCrossingOnRegisterInterface : off
	ClockRatePipelining : inherit
	ConstrainedOutputPipeline : 0
	DistributedPipelining : inherit
	DSPStyle : none
	ExposeDUTCEOutPort : off
	ExposeDUTClockEnablePort : off
	FlattenHierarchy : inherit
	GenerateDefaultAXI4Slave : on
	IncludeDataCaptureControlLogicEnable : off
	InputPipeline : 0
	IPCoreAdditionalFiles : 
	IPCoreName : 
	IPCoreVersion : 
	IPDataCaptureBufferSize : 128
	IPDataCaptureSequenceDepth : 1
	OutputPipeline : 0
	ProcessorFPGASynchronization : 
	RegisterInterfaceReadPipeline : 0
	SharingFactor : 0
	StreamingFactor : 0

Input Arguments

path — Path to block or subsystem in current model

string scalar | character vector

Path to a block or subsystem in the current model.

"all" — Display all HDL block properties

"all" | 'all'

If you specify "all", hdldispblkparams displays the names and values of all HDL properties of the specified block or subsystem.

Version History

Introduced in R2010b