Run and Verify IP Core
Run and verify the generated bitstream from your IP core design on your target hardware. The input is a generated bitstream for the FPGA portion of your device. The output is a simulated and verified design running on your target FPGA. For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.
Target Connection Interfaces
|Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface (Since R2020b)
|Write data to IP core or read data from IP core using AXI4-Stream interface (Since R2020b)
|Access memory regions on your FPGA or SoC hardware (Since R2023a)
|Maps a DUT port to specified AXI4 interface in HDL IP core (Since R2020b)
|Write data to a DUT port from MATLAB (Since R2020b)
|Reads output data and returns it with the port data type and dimension (Since R2020b)
|Write data to memory regions on FPGA or SoC hardware (Since R2023a)
|Read data from memory regions on FPGA or SoC hardware (Since R2023a)
|Read data from memory regions on FPGA or SoC hardware by using offset address (Since R2023b)
|Write data to memory regions on FPGA or SoC hardware by using the offset address (Since R2023b)
|Release the hardware resources associated with the fpga object (Since R2020b)
|Run command in Linux shell on SoC board (Since R2022a)
|Transfer file from SoC board to host computer (Since R2022a)
|Transfer file from host computer to SoC board (Since R2022a)
|Delete file on SoC board (Since R2022a)
|List directory contents on SoC board (Since R2022a)
|Program FPGA and set corresponding device tree from processor on SoC board (Since R2022a)
- Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
- Generate and Manage Host Interface Scripts
Understand what a host interface script is and learn how to generate and manage host interface scripts.
- Create Host Interface Script to Control and Rapidly Prototype HDL IP Core
Create and author a host interface script by configuring interfaces and port mapping information to control HDL IP core.
- Use JTAG AXI Manager to Control HDL Coder Generated IP Core
This example shows how to specify automatic insertion of the HDL Verifier™ AXI Manager IP into a reference design.
- Inspect the Written Values of AXI4 Slave Registers by Using the Readback Methods
This example describes the different techniques to read the AXI4 slave input registers in your design.
- Debug IP Core Using FPGA Data Capture
This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.
- Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.