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Synthesis Objective to Tcl Command Mapping

The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink® subsystem and the FPGA design process, such as:

  • Checking the model for HDL code generation compatibility and automatically fixing incompatible settings.

  • Generation of HDL code, a test bench, and scripts to build and run the code and test bench.

  • Generation of cosimulation or SystemVerilog DPI test benches and code coverage (requires HDL Verifier™).

  • Synthesis and timing analysis through integration with third-party synthesis tools.

  • Back-annotation of the model with critical path information and other information obtained during synthesis.

  • Complete automated workflows for selected FPGA development target devices, including FPGA-in-the-loop simulation (requires HDL Verifier), and the Simulink Real-Time™ FPGA I/O workflow.

When you specify a synthesis objective in the HDL Workflow Advisor Synthesis objective field, or in the HDL Workflow CLI workflow hdlcoder.Objective, the HDL Coder™ software generates Tcl commands that are specific to your synthesis tool.

Altera Quartus II

Synthesis objectiveTcl Commands
Area Optimizedset_global_assignment -name OPTIMIZATION_TECHNIQUE "Area"
set_global_assignment -name FITTER_EFFORT "Standard Fit"
Compile Optimizedset_global_assignment -name OPTIMIZATION_TECHNIQUE "Balanced"
set_global_assignment -name FITTER_EFFORT "Fast Fit"
Speed Optimizedset_global_assignment -name OPTIMIZATION_TECHNIQUE "Speed"
set_global_assignment -name FITTER_EFFORT "Standard Fit"

Xilinx Vivado 2014.4

If your tool version is different, the Tcl commands are slightly different.

Synthesis objectiveTcl Commands
Area Optimizedset_property strategy {Vivado Synthesis Defaults} [get_runs synth_1]
set_property strategy "Area_Explore" [get_runs impl_1]
Compile Optimizedset_property strategy "Flow_RuntimeOptimized" [get_runs synth1]
set_property strategy "Flow_Quick" [get_runs impl_1]
Speed Optimizedset_property strategy {Vivado Synthesis Defaults} [get_runs synth_1]
set_property strategy "Performance_Explore" [get_runs impl_1]

Xilinx ISE 14.7 with PlanAhead

If your tool version is different, the Tcl commands are slightly different.

Synthesis objectiveTcl Commands
Area Optimizedset_property strategy "AreaReduction" [get_runs synth_1]
set_property strategy "MapCoverArea" [get_runs impl_1]
Compile Optimizedset_property strategy "{XST Defaults}" [get_runs synth_1]
set_property strategy "{ISE Defaults}" [get_runs impl_1]
Speed Optimizedset_property strategy "TimingWithIOBPacking" [get_runs synth_1]
set_property strategy "MapTiming" [get_runs impl_1]

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