Get Started with Filter Design HDL Coder

Filter Design HDL Coder™ generates synthesizable, portable VHDL^® and Verilog^® code for implementing fixed-point filters designed with MATLAB^® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.

Tutorials

• Basic FIR Filter
  

  Design a basic quantized discrete-time FIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.

• Optimized FIR Filter
  

  Design an optimized FIR filter, generate Verilog code for the filter, and verify the Verilog code with a generated test bench.

• IIR Filter
  

  Design an IIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.

About Filter Design and HDL Code Generation

• Automated HDL Code Generation
  

  Overview of filter design-based HDL code generation.

Featured Examples

HDL Butterworth Filter

Illustrates how to generate HDL code for a 5th order Butterworth filter. The cutoff-frequency for this filter is very low relative to the sample rate, leading to a filter that is difficult to make practical. Also, small input (8-bit) and output (9-bit) word sizes cause the quantized filter to require scaling to be realizable.

Open Live Script

HDL Minimum Phase FIRT Filter

Illustrates how to generate HDL code for a minimum phase FIRT filter with 10-bit input data. This is a bandpass filter with sample rate of 96 kHz and passband from approximately 19 kHz to 29 kHz. This type of filter is commonly used in feedback loops where linear phase is not sufficient and minimum phase or as close as is achievable is required.

Open Live Script