setCaptureConditionComparisonOperator

Configure operator that compares individual signal values within capture condition

Since R2022a

Syntax

setCaptureConditionComparisonOperator(DC,name,operator)

Description

Add-On Required: This feature requires one of these add-ons.

• HDL Verifier Support Package for Intel FPGA Boards
• HDL Verifier Support Package for AMD FPGA and SoC Devices

setCaptureConditionComparisonOperator(DC,name,operator) configures a comparison operator operator that compares individual signal values within the capture condition. DC is a customized data capture object. name is the name of a capture component signal.

Examples

Set Up Capture Condition Using Comparison Operator

This example uses a customized data capture object, DC, that defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic.

DC.EnableCaptureCtrl = true;

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IP core using the FPGA Data Capture Component Generator tool.

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7.

setCaptureCondition(DC,'A',true,'High');
setCaptureCondition(DC,'B',true,7);
setCaptureConditionComparisonOperator(DC,'B','>');

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

name — Name of capture component signal

character vector

Name of a capture component signal, specified as a character vector. This name must match one of the signal names configured on creation of the input System object DC. The signal must be configured as a possible trigger signal.

operator — Operator to compare signals within capture condition

== (default) | != | < | > | <= | >=

Operator to compare signals within the capture condition, specified as one of these operators: ==, !=, <, >, <=, or >=.

The capture condition comprises value comparisons of one or more signals. For a multibit signal, specify one of these operators: == (default), !=, <, >, <=, or >=. For a capture condition containing X or x (which indicate bits for the function to ignore), specify either the == or != operators. For a logical signal, specify either the == or != operators. For details on capture conditions, see Capture Conditions.

Version History

Introduced in R2022a