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The TLM Generation Process

After you obtain the TLM component files generated by HDL Verifier™ software, you can compile the TLM component and the optional test bench with OSCI SystemC™ libraries and the OSCI TLM libraries. To do so, use the makefile supplied by HDL Verifier to create your virtual platform executable (e.g., mysimulation.exe).

The following diagram illustrates the complete set of articles you can generate including the TLM component, the TLM component test bench, and the set of test vectors to be executed by the test bench. Simulink® generates these vectors while performing model execution when you verify the TLM component from within Simulink (see Run TLM Component Test Bench).


This feature requires the ASIC Testbench for HDL Verifier add-on.

The following general workflow describes the process for creating an OSCI-compatible TLM component representing the Simulink algorithm:

  1. Create Simulink model representing algorithm.

  2. Select required architectural model (i.e., virtual platform model) parameters via the Simulink Configuration Parameters dialog box. See Subsystem Guidelines and Limitations.

  3. (Optional) If you want, restore any desired configuration sets at this time. Because the topic of configuration sets is outside the scope of this workflow description, refer to the section Model Reference Basics (Simulink) in the Simulink documentation.

  4. Initiate code generation.

  5. Save configuration options with the model for future use.