Frequency Division Using Fractional Clock Divider with Accumulator
Open the model fractionalClockDivider_w_Accumulator
. The model consists of a Pulse Generator and a Fractional Clock Divider with Accumulator block.
model='fractionalClockDivider_w_Accumulator';
open_system(model)
The period of the incoming pulse at the clk in port is 4e-7
s. So, the incoming signal has a frequency of 2.5
MHz. The div-by value is set at 2.5
.
Run the simulation for 1e-4
s. The frequency of the output signal is 1.002
MHz.
sim(model);