Visualize and Interpret Parallel Link Project Analysis Results

Visualize and interpret the network characterization and statistical and time domain analysis results

Using the Parallel Link Designer app, you can analyze the results of network characterization and statistical and time domain analysis. The app reports various metrics and visualizations including the eye diagrams, bathtubs, and contours to provide insight into your design. You can also perform waveform and timing analysis.

You can also use data mining and advanced visualization techniques to narrow down the large simulation data to focus on the area of your interest.

Topics

Network, Statistical, and Time-Domain Analysis

Network Characterization Results
Table of data and waveforms to view in the Network tab after performing network characterization.
Statistical Analysis Results
Table of data and waveforms to view in the Statistical tab after performing statistical analysis.
Time Domain Analysis Results
Table of data and waveforms to view in the time domain tab after performing time domain analysis.
Interpreting Waveform, Eye Diagram, and Timing Results
Waveform, eye diagram, and timing results interpretations in Parallel Link Designer.
Eye Measurement and Reporting
Measure and report eye diagram metrics.
Widebus Crosstalk Analysis
Pre-layout crosstalk analysis in the Parallel Link Designer app.

Waveform Analysis

Waveform Analysis
Analyze waveform overshoot and other quality metrics.
Waveform Analysis Parameters and Thresholds
Learn about the parameters and thresholds used in waveform analysis using the Parallel Link Designer app.
Waveform Reports
Results of waveform and timing analysis.

Timing Analysis

Timing Analysis
Static timing analysis to compute setup and hold margins on synchronous and source-synchronous transfers.
Timing Analysis Reports
Results of timing analysis.
Clock Skew in Synchronous Interface Timing
Learn how calculate dynamic and user-defined clock skews in synchronous interfaces.
Clock Skew in Source-Synchronous Interface Timing
Learn how calculate setup and hold margins in source-synchronous interfaces.
Clock Delay Through Buffers and PLLs
Learn how to calculate clock delays through buffers and PLLs.

Data Mining and Advanced Visualization

Managing Simulation Data and Results
Quickly and efficiently sort through the simulation data and results of the link design project.
Advanced Visualization Using Signal Integrity Viewer
Plot frequency and time domain waveforms and results against single or multiple variables.

Featured Examples

DDRx Timing and Waveform Mask Analysis

Use the Parallel Link Designer app to perform timing analysis for the DDR (Double Data Rate) family of memory interface protocols. You can use either Setup and Hold margins or by waveform eye-diagram compliance masks to perform the timing analysis. The DDR Memory Down (DDR4_MD) example kit uses both timing and waveform mask analysis. Specifically for DDR4 systems, timing analysis is performed on clock-address/command interface, and waveform compliance masks are applied to strobe-data(DQS-DQ) interface. Other DDR types may use only timing analysis, or only waveform mask analysis or a blend depending on individual standards.

Open Live Script