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Post-Layout Verification of Parallel Link Projects

Verify the layout design of your system against design guidelines or specification rules

Post-layout verification allows you to verify the performance of your actual routed system against the design guidelines or specification rules. You can edit the vias and stackups and control the padstack models. You can also verify your design using PCB models. You can create topologies from extracted PCB data for pre-layout analysis.


You need a RF PCB Toolbox™ license for the post-layout workflow.


Parallel Link DesignerAnalyze PCB designs for parallel link applications (Since R2021b)
Signal Integrity ViewerView the signal integrity results of Serial Link Designer or Parallel Link Designer apps (Since R2021b)