Discrete FIR Filter

Model FIR filters

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Libraries:
Simulink / Discrete
HDL Coder / Discrete
HDL Coder / HDL Floating Point Operations

Description

The Discrete FIR Filter block independently filters each channel of the input signal with the specified digital FIR filter. The block can implement static filters with fixed coefficients, and time-varying filters with coefficients that change over time. You can tune the coefficients of a static filter during simulation.

This block filters each channel of the input signal independently over time. The Input processing parameter allows you to specify whether the block treats each element of the input as an independent channel (sample-based processing), or each column of the input as an independent channel (frame-based processing). To perform frame-based processing, you must have a DSP System Toolbox™ license.

The output dimensions equal the input dimensions, except when you specify a matrix of filter taps for the Coefficients parameter. When you do so, the output dimensions depend on the number of different sets of filter taps you specify.

This block supports custom state attributes to customize and generate code more efficiently. For an example, see Custom State Attributes in Discrete FIR Filter block. Under certain conditions, the block also supports SIMD code generation. For details, see Code Generation.

The outputs of this block numerically match the outputs of the DSP System Toolbox Digital Filter Design (DSP System Toolbox) block.

This block supports the Simulink^® state logging feature. For more information, see State.

Filter Structure Support

You can change the filter structure implemented with the Discrete FIR Filter block by selecting one of the following from the Filter structure parameter:

• Direct form

• Direct form symmetric

• Direct form antisymmetric

• Direct form transposed

• Lattice MA

You must have an available DSP System Toolbox license to run a model with any of these filter structures other than Direct form.

For more information on the filter structures, see Algorithms.

Specifying Initial States

The Discrete FIR Filter block initializes the internal filter states to zero by default, which has the same effect as assuming that past inputs and outputs are zero. You can optionally use the Initial states parameter to specify nonzero initial conditions for the filter delays.

To determine the number of initial states you must specify and how to specify them, see the table on valid initial states. The Initial states parameter can take one of the forms described in the next table.

Valid Initial States

Initial Condition	Description
Scalar	The block initializes all delay elements in the filter to the scalar value.
Vector or matrix (for applying different delay elements to each channel)	Each vector or matrix element specifies a unique initial condition for a corresponding delay element in a corresponding channel: The vector length equals the product of the number of input channels and the number of delay elements in the filter, #_of_filter_coeffs-1 (or #_of_reflection_coeffs for Lattice MA). The matrix must have the same number of rows as the number of delay elements in the filter, #_of_filter_coeffs-1 (#_of_reflection_coeffs for Lattice MA), and must have one column for each channel of the input signal.

Examples

Cochlear Implant Speech Processor

Simulate the design of a cochlear implant that can be placed in the inner ear of a profoundly deaf person to restore partial hearing. Signal processing is used in cochlear implant development to convert sound to electrical pulses. The pulses can bypass the damaged parts of a deaf person's ear and be transmitted to the brain to provide partial hearing.

Active Noise Control with Simulink Real-Time

Design a real-time active noise control system using a Speedgoat® Simulink® Real-Time™ target.

Acoustic Noise Cancellation (LMS)

Use the least mean square (LMS) algorithm to subtract noise from an input signal. The example uses a preconfigured Simulink® model. The LMS Filter block in the dspanc model models an adaptive filter that uses the reference signal at its Input port and the desired signal at the Desired port to automatically match the filter response. The LMS Filter block subtracts the filtered noise from the original signal. As the filter converges, the resultant error signal contains only the original signal.

Use the Fixed-Point Tool to Rescale a Fixed-Point Model

Show you how to use the Fixed-Point Tool to refine the scaling of fixed-point data types associated with the feedback controller model fxpdemo_feedback. The Fixed-Point Tool enables multiple workflows for converting a model to use fixed-point data types.

Programmable FIR Filter for FPGA

Implement a programmable FIR filter for hardware. You can program the filter to the required response by loading the coefficients into internal registers using a memory-style interface.

Ports

Input

In — Input signal

scalar | vector | matrix

Input signal to filter, specified as a scalar, vector, or matrix.

The Discrete FIR Filter block accepts real and complex signals of any numeric data type supported by Simulink.

Dependencies

When you set Coefficient source to Dialog parameters, the port for the input signal is unlabeled. When you set Coefficient source to Input port, the port for the input signal is labeled In.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Complex Number Support: Yes

Num — Filter coefficients

scalar | vector

Specify the filter coefficients as a scalar or a vector. When you specify a row vector of filter taps, the block applies a single filter to the input. To apply multiple filters to the input, specify the coefficients in the matrix form through the Coefficients parameter.

Dependencies

To enable this port, set Coefficient source to Input port.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

External reset — External reset signal

scalar

External reset signal, specified as a scalar. When the specified trigger event occurs, the block resets the states to their initial conditions.

Tip

The icon for this port changes based on the value of the External reset parameter.

Dependencies

To enable this port, set External reset to Rising, Falling, Either, Level, or Level hold.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

⎍ — Enable signal

scalar

Enable signal, specified as a scalar. This port can control execution of the block. The block is enabled when the input to this port is nonzero, and is disabled when the input is 0. The value of the input is checked at the same time step as the block execution.

Dependencies

To enable this port, select the Show enable port check box.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Output

Port_1 — Filtered output signal

scalar | vector | matrix

Filtered output signal, returned as a scalar, vector, or a matrix. The Discrete FIR Filter block outputs real and complex signals of any numeric data type supported by Simulink.

When the input to the block is fixed-point, the data type of the block output is determined based on the value you specify in the Output parameter. When the input is floating-point, the output data type matches the input data type since floating-point inheritance takes precedence over the fixed-point settings.

When you set Sample time to -1, sample time of the output signal is same as the sample time of the input signal In.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Parameters

Main

Coefficient source — Source of coefficients

Dialog parameters (default) | Input port

Choose to specify the filter coefficients using tunable dialog parameters or through an input port, which is useful for time-varying coefficients.

Programmatic Use

Block Parameter: CoefSource

Type: character vector

Values: 'Dialog parameters' | 'Input port'

Default: 'Dialog parameters'

Filter structure — Filter structure

Direct form (default) | Direct form symmetric | Direct form antisymmetric | Direct form transposed | Lattice MA

Select the filter structure you want the block to implement. For more information, see Algorithms.

Dependencies

You must have an available DSP System Toolbox license to run a model with a Discrete FIR Filter block that implements any filter structure other than Direct form.

Programmatic Use

Block Parameter: FilterStructure

Type: character vector

Values: 'Direct form' | 'Direct form symmetric' | 'Direct form antisymmetric' | 'Direct form transposed' | 'Lattice MA'

Default: 'Direct form'

Coefficients — Filter coefficients

[0.5 0.5] (default) | scalar | vector | matrix

Specify the filter coefficients as a scalar, vector or a matrix.

When you specify a row vector of filter taps, the block applies a single filter to the input. To apply multiple filters to the same input, specify a matrix of coefficients, where each row represents a different set of filter taps. To implement multiple filters, set Filter structure to Direct form and the input must be a scalar.

Dependencies

To enable this parameter, set Coefficient source to Dialog parameters.

Programmatic Use

Block Parameter: Coefficients

Type: character vector

Values: vector

Default: '[0.5 0.5]'

Input processing — Sample- or frame-based processing

Elements as channels (sample based) (default) | Columns as channels (frame based)

Specify whether the block performs sample- or frame-based processing. You can select one of the following options:

• Elements as channels (sample based) — Treat each element of the input as an independent channel (sample-based processing).

• Columns as channels (frame based) — Treat each column of the input as an independent channel (frame-based processing).

  Note

  Frame-based processing requires a DSP System Toolbox license.

  For more information, see Sample- and Frame-Based Concepts (DSP System Toolbox).

Programmatic Use

Block Parameter: InputProcessing

Type: character vector

Values: 'Columns as channels (frame based)' | 'Elements as channels (sample based)'

Default: 'Elements as channels (sample based)'

Initial states — Initial conditions of filter states

0 (default) | scalar | vector | matrix

Specify the initial conditions of the filter states. To learn how to specify initial states, see Specifying Initial States.

Programmatic Use

Block Parameter: InitialStates

Type: character vector

Values: scalar | vector | matrix

Default: '0'

Show enable port — Create enable port

off (default) | on

Select to control execution of this block with an enable port. The block is considered enabled when the input to this port is nonzero, and is disabled when the input is 0. The value of the input is checked at the same time step as the block execution.

Programmatic Use

Block Parameter: ShowEnablePort

Type: character vector

Values: 'off' | 'on'

Default: 'off'

External reset — External state reset

None (default) | Rising | Falling | Either | Level | Level hold

Specify the trigger event to use to reset the states to the initial conditions.

Reset Mode	Behavior
None	No reset
Rising	Reset on a rising edge
Falling	Reset on a falling edge
Either	Reset on either a rising or falling edge
Level	Reset in either of these cases: When the reset signal is nonzero at the current time step When the reset signal value changes from nonzero at the previous time step to zero at the current time step
Level hold	Reset when the reset signal is nonzero at the current time step

Programmatic Use

Block Parameter: ExternalReset

Type: character vector

Values: 'None' | 'Rising' | 'Falling' | 'Either' | 'Level' | 'Level hold'

Default: 'None'

Sample time (-1 for inherited) — Interval between samples

-1 (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Dependencies

This parameter is visible only if you set it to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime

Type: string scalar or character vector

Default: "-1"

Data Types

Tap sum — Tap sum data type

Inherit: Same as input (default) | Inherit: Inherit via internal rule | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16,0) | <data type expression>

Specify the tap sum data type of a direct form symmetric or direct form antisymmetric filter, which is the data type the filter uses when it sums the inputs prior to multiplication by the coefficients. You can set it to:

• A rule that inherits a data type, for example, Inherit: Inherit via internal rule

• A built-in integer, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

Dependencies

This parameter is only visible when you set the Filter structure to Direct form symmetric or Direct form antisymmetric.

Programmatic Use

Block Parameter: TapSumDataTypeStr

Type: character vector

Values: 'Inherit: Same as input' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Same as input'

Coefficients — Coefficient data type

Inherit: Same wordlength as input (default) | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16,0) | <data type expression>

Specify the coefficient data type. You can set it to:

• A rule that inherits a data type, for example, Inherit: Same word length as input

• A built-in integer, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

Block Parameter: CoefDataTypeStr

Type: character vector

Values: 'Inherit: Same word length as input'| 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16)' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Same wordlength as input'

Coefficients minimum — Minimum value of coefficients

[] (default) | scalar

Specify the minimum value that a filter coefficient should have. The default value is [] (unspecified). Simulink software uses this value to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters)

• Automatic scaling of fixed-point data types

Programmatic Use

Block Parameter: CoeffMin

Type: character vector

Values: scalar

Default: '[]'

Coefficients maximum — Maximum value of coefficients

[] (default) | scalar

Specify the maximum value that a filter coefficient should have. The default value is [] (unspecified). Simulink software uses this value to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters)

• Automatic scaling of fixed-point data types

Programmatic Use

Block Parameter: CoeffMax

Type: character vector

Values: scalar

Default: '[]'

Product output — Product output data type

Inherit: Inherit via internal rule (default) | Inherit: Same as input | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16,0) | <data type expression>

Specify the product output data type. You can set it to:

• A rule that inherits a data type, for example, Inherit: Inherit via internal rule

• A built-in data type, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

Block Parameter: ProductDataTypeStr

Type: character vector

Values: 'Inherit: Inherit via internal rule' | 'Inherit: Same as input' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Inherit via internal rule'

Accumulator — Accumulator data type

Inherit: Inherit via internal rule (default) | Inherit: Same as input | Inherit: Same as product output | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16,0) | <data type expression>

Specify the accumulator data type. You can set it to:

• A rule that inherits a data type, for example, Inherit: Inherit via internal rule

• A built-in data type, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

Block Parameter: AccumDataTypeStr

Type: character vector

Values: 'Inherit: Inherit via internal rule' | 'Inherit: Same as input' | 'Inherit: Same as product output' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Inherit via internal rule'

State — State data type

Inherit: Same as accumulator (default) | Inherit: Same as input | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16,0) | <data type expression>

Specify the state data type. You can set it to:

• A rule that inherits a data type, for example, Inherit: Same as accumulator

• A built-in integer, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

Dependencies

To enable this parameter, set the Filter structure to Lattice MA.

Programmatic Use

Block Parameter: StateDataTypeStr

Type: character vector

Values: 'Inherit: Same as accumulator' | 'Inherit: Same as input' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Same as accumulator'

Output — Output data type

Inherit: Same as accumulator (default) | Inherit: Same as input | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Specify the output data type. You can set it to:

• A rule that inherits a data type, for example, Inherit: Same as accumulator

• A built-in data type, for example, int8

• A data type object, for example, a Simulink.NumericType object

• An expression that evaluates to a data type, for example, fixdt(1,16,0)

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

When the input to the block is floating-point, the output data type matches the input data type since floating-point inheritance takes precedence over the fixed-point settings.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: Same as accumulator' | 'Inherit: Same as input' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | 'fixdt(1,16)' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'Inherit: Same as accumulator'

Output minimum — Minimum output value for range checking

[] (default) | scalar

Lower value of the output range that Simulink checks.

Simulink uses the minimum to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.

• Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).

• Automatic scaling of fixed-point data types.

• Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).

Note

Output minimum does not saturate or clip the actual output signal. Use the Saturation block instead.

Programmatic Use

Block Parameter: OutMin

Type: character vector

Values: '[ ]'| scalar

Default: '[ ]'

Output maximum — Maximum output value for range checking

[] (default) | scalar

Upper value of the output range that Simulink checks.

Simulink uses the maximum value to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.

• Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).

• Automatic scaling of fixed-point data types.

• Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).

Note

Output maximum does not saturate or clip the actual output signal. Use the Saturation block instead.

Programmatic Use

Block Parameter: OutMax

Type: character vector

Values: '[ ]'| scalar

Default: '[ ]'

Lock data type settings against changes by the fixed-point tools — Prevent fixed-point tools from overriding data types

off (default) | on

Select to lock data type settings of this block against changes by the Fixed-Point Tool and the Fixed-Point Advisor. For more information, see Lock the Output Data Type Setting (Fixed-Point Designer).

Programmatic Use

Block Parameter: LockScale

Values: 'off' | 'on'

Default: 'off'

Integer rounding mode — Rounding mode for fixed-point operations

Floor (default) | Ceiling | Convergent | Nearest | Round | Simplest | Zero

Specify the rounding mode for fixed-point operations. For more information, see Rounding (Fixed-Point Designer).

Programmatic Use

Block Parameter: RndMeth

Type: character vector

Values: 'Ceiling' | 'Convergent' | 'Floor' | 'Nearest' | 'Round' | 'Simplest' | 'Zero'

Default: 'Floor'

Saturate on integer overflow — Method of overflow action

off (default) | on

Specify whether overflows saturate or wrap.

Action	Rationale	Impact on Overflows	Example
Select this check box (on).	Your model has possible overflow, and you want explicit saturation protection in the generated code.	Overflows saturate to either the minimum or maximum value that the data type can represent.	The maximum value that the int8 (signed, 8-bit integer) data type can represent is 127. Any block operation result greater than this maximum value causes overflow of the 8-bit integer. With the check box selected, the block output saturates at 127. Similarly, the block output saturates at a minimum output value of -128.
Do not select this check box (off).	You want to optimize efficiency of your generated code. You want to avoid overspecifying how a block handles out-of-range signals. For more information, see Troubleshoot Signal Range Errors.	Overflows wrap to the appropriate value that is representable by the data type.	The maximum value that the int8 (signed, 8-bit integer) data type can represent is 127. Any block operation result greater than this maximum value causes overflow of the 8-bit integer. With the check box cleared, the software interprets the overflow-causing value as int8, which can produce an unintended result. For example, a block result of 130 (binary 1000 0010) expressed as int8, is -126.

When you select this check box, saturation applies to every internal operation on the block, not just the output, or result. Usually, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.

Programmatic Use

Block Parameter: SaturateOnIntegerOverflow

Type: character vector

Values: 'off' | 'on'

Default: 'off'

Block Characteristics

Data Types	double | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	no
Variable-Size Signals	yes
Zero-Crossing Detection	no

More About

Filter Structure Diagrams for Fixed-Point Signals

The following diagrams show the filter structure and the data types used within the Discrete FIR Filter block for fixed-point signals.

Direct Form

You cannot specify the state data type on the block mask for this structure because the input states have the same data types as the input.

Direct Form Symmetric

You cannot specify the state data type on the block mask for this structure because the input states have the same data types as the input.

Direct Form Antisymmetric

You cannot specify the state data type on the block mask for this structure because the input states have the same data types as the input.

Direct Form Transposed

Lattice MA

Algorithms

These are the structure diagrams used within the Discrete FIR Filter block.

Direct Form

Direct Form Symmetric

It is assumed that the filter coefficients are symmetric. The block only uses the first half of the coefficients for filtering.

Direct Form Antisymmetric

It is assumed that the filter coefficients are antisymmetric. The block only uses the first half of the coefficients for filtering.

Direct Form Transposed

States are complex when either the inputs or the coefficients are complex.

Lattice MA

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports custom state attributes to customize and generate code more efficiently. To access or set these attributes, open the Model Data Editor. On the Modeling tab, click Model Data Editor. For an example, see Custom State Attributes in Discrete FIR Filter block.

Generate SIMD code using Intel AVX2 code replacement library

Note

Requires Embedded Coder^® license

The Discrete FIR Filter block supports SIMD code generation using Intel AVX2 code replacement library under these conditions:

• Filter structure is set to Direct form or Direct form transposed.

• Input processing is set to Columns as channels (frame based).

• Input signal is real-valued with real filter coefficients.

• When Filter structure is set to Direct form, input signal is complex-valued with real or complex filter coefficients.

• Input signal has a data type of single or double.

Generate SIMD code by leveraging target hardware instruction set extensions (since R2022b)

Note

Requires Simulink Coder™ or Embedded Coder license

You can generate SIMD code for the Discrete FIR Filter block on all Intel^® platforms and ARM^® Cortex^®-A processors by using the model configuration parameter Leverage target hardware instruction set extensions under these conditions:

• You set Filter structure to Direct form

• You set Input processing to Columns as channels (frame based)

• Input signal is real-valued with real filter coefficients

• Input signal is real-valued or complex-valued.

• Data type of the input signal is single (ARM Cortex-A processors)

• Data type of the input signal is single or double (Intel platforms)

In addition, configure your model appropriately.

In the Modeling tab of the Simulink model window, click Model Settings and configure these parameters under Code Generation.

• In the Optimization pane:

  • Provide a specific instruction set in the Leverage target hardware instruction set extensions parameter.

  • Select the Optimize reductions parameter.

  • Under Optimization levels, set Level to Maximum and Priority to Maximize execution speed.

• In the Interface pane, under Software environment, clear non-finite numbers.

To generate SIMD code from this block using this workflow, see Use Intel AVX2 Code Replacement Library to Generate SIMD Code from Simulink Blocks (DSP System Toolbox).

For computationally intensive operations on supported blocks, SIMD intrinsics can significantly improve the performance of the generated code on Intel platforms. For more details, see Optimize Code for Reduction Operations by Using SIMD (Simulink Coder). To generate SIMD code from this block, see Generate SIMD Code from Simulink Blocks for Intel Platforms (Simulink Coder).

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

For hardware-friendly valid and reset control signals, and to model exact hardware latency behavior in Simulink, use the Discrete FIR Filter (DSP HDL Toolbox) block instead.

To reduce area or increase speed, the Discrete FIR Filter block supports either block-level optimizations or subsystem-level optimizations. For details of available block-level optimization parameters, see Block Optimizations. When you enable block optimizations, the block cannot participate in subsystem optimizations. Use block optimizations when your design is a single one-channel filter. Use subsystem optimizations to share resources across multiple channels or multiple filters. For the block to participate in subsystem-level optimizations, set the Architecture to Fully parallel. See Subsystem Optimizations for Filters (HDL Coder).

Multichannel Filter Support

HDL Coder supports the use of vector inputs to Discrete FIR Filter blocks, where each element of the vector represents an independent channel.

1. Connect a vector signal to the Discrete FIR Filter block input port.

2. Specify Input processing as Elements as channels (sample based).

3. To reduce area by sharing the filter kernel between channels, set the ChannelSharing property to the number of channels.

Programmable Filter Support

HDL Coder supports programmable filters for Discrete FIR Filter blocks.

1. On the filter block mask, set Coefficient source to Input port.

2. Connect a vector signal to the Num coefficient port.

Programmable filters are not supported for:

• distributed arithmetic (DA)

• CoeffMultipliers set to csd or factored-csd

Frame-Based Input Support

HDL Coder supports the use of vector inputs to Discrete FIR Filter blocks, where each element of the vector represents a sample in time. You can use an input vector of up to 512 samples. The frame-based implementation supports fixed-point input and output data types, and uses full-precision internal data types. You can use real input signals with real coefficients, complex input signals with real coefficients, or real input signals with complex coefficients. You can also use frame-based input with programmable coefficients.

1. Connect a vector signal to the Discrete FIR Filter block input port.

2. Specify Input processing as Columns as channels (frame based), and set Filter structure to Direct form or Direct form transposed. For frame-based input with programmable coefficients, set Filter structure to Direct form.

3. Right-click the block and open HDL Code > HDL Block Properties. Set the Architecture to Frame Based. The block implements a direct form parallel HDL architecture. Other architectures, including fully- or partly-serial, are not supported. See Frame-Based Architecture (HDL Coder).

Frame-based input filters are not supported for:

• Optional block-level reset and enable control signals

• Resettable and enabled subsystems

• Complex input signals with complex coefficients. You can use either complex input signals and real coefficients, or complex coefficients and real input signals.

• Multichannel input

• Sharing and streaming optimizations

• distributed arithmetic (DA)

Control Ports

You can generate HDL code for filters with or without the optional enable port, and with or without the optional reset port.

Complex Data Support

You can use any combination of complex input and complex coefficients with fully-parallel filter structures, when you use non-frame-based input data.

Complex coefficients are not supported with serial filter architectures.

When you use frame-based input data you can use either complex input signals and real coefficients, or complex coefficients and real input signals.

You cannot use distributed arithmetic (DA) or CoeffMultipliers set to csd or factored-csd with complex coefficients.

Block Optimizations

Area and Speed Optimizations
Serial Architecture	To use block-level optimizations to reduce hardware resources, set Architecture to one of the serial options. See HDL Filter Architectures (HDL Coder). When you specify SerialPartition and ReuseAccum for a Discrete FIR Filter block, set Filter structure to Direct form, Direct form symmetric, or Direct form antisymmetric. The Direct form transposed structure is not supported with serial architectures.
Distributed Arithmetic	To minimize multipliers by replacing them with LUTs and shift registers, use a distributed arithmetic (DA) filter implementation. See Distributed Arithmetic for HDL Filters (HDL Coder). When you select the Distributed Arithmetic (DA) architecture and use the DALUTPartition and DARadix distributed arithmetic properties, set Filter structure to Direct form, Direct form symmetric, or Direct form antisymmetric. The Direct form transposed structure is not supported with distributed arithmetic.
Multichannel Area Reduction	To share filter logic between channels, set the ChannelSharing property to the number of channels. Using ChannelSharing excludes the filter from other optimizations. You can achieve the same logic sharing across all eligible logic in a subsystem by using the StreamingFactor property. This option also enables the filter to participate in other subsystem optimizations. See the Streaming section of Subsystem Optimizations for Filters (HDL Coder).
Pipelining	To improve clock speed, use AddPipelineRegisters to use a pipelined adder tree rather than the default linear adder. You can also specify the number of pipeline stages before and after the multipliers. See HDL Filter Architectures (HDL Coder).

HDL Filter Properties
AddPipelineRegisters	Insert a pipeline register between stages of computation in a filter. See also AddPipelineRegisters (HDL Coder).
ChannelSharing	For a multichannel filter, generate a single filter implementation to be shared between channels. See also ChannelSharing (HDL Coder).
CoeffMultipliers	Specify the use of canonical signed digit (CSD) optimization to decrease filter area by replacing coefficient multipliers with shift-and-add logic. When you choose a fully parallel filter implementation, you can set CoeffMultipliers to csd or factored-csd. The default is multipliers, which retains multipliers in the HDL. See also CoeffMultipliers (HDL Coder).
DALUTPartition	Specify distributed arithmetic partial-product LUT partitions as a vector of the sizes of each partition. The sum of all vector elements must be equal to the filter length. The maximum size for a partition is 12 taps. Set DALUTPartition to a scalar value equal to the filter length to generate DA code without LUT partitions. See also DALUTPartition (HDL Coder).
DARadix	Specify how many distributed arithmetic bit sums are computed in parallel. A DA radix of 8 (2^3) generates a DA implementation that computes three sums at a time. The default value is 2^1, which generates a fully serial DA implementation. See also DARadix (HDL Coder).
MultiplierInputPipeline	Specify the number of pipeline stages to add at filter multiplier inputs. See also MultiplierInputPipeline (HDL Coder).
MultiplierOutputPipeline	Specify the number of pipeline stages to add at filter multiplier outputs. See also MultiplierOutputPipeline (HDL Coder).
ReuseAccum	Enable or disable accumulator reuse in a serial filter implementation. Set ReuseAccum to on to use a cascade-serial implementation. See also ReuseAccum (HDL Coder).
SerialPartition	Specify partitions for partly serial or cascade-serial filter implementations as a vector of the lengths of each partition. For a fully serial implementation, set this parameter to the length of the filter. See also SerialPartition (HDL Coder).

HDL Block Properties
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

• HDL code generation is not supported for:

  • Unsigned input data.

  • Nonzero initial states. You must set Initial states to 0.

  • Filter Structure: Lattice MA.

• CoeffMultipliers options are supported only when using a fully parallel architecture. When you select a serial architecture, CoeffMultipliers is hidden from the HDL Block Properties dialog box.

PLC Code Generation
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Fixed-Point Conversion
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Version History

Introduced in R2008a

R2023b: Generate SIMD Code for Complex Signals

In R2023b, if you have Embedded Coder, you can generate SIMD code for the Discrete FIR Filter block when the input signal is complex-valued by using the model configuration parameter Leverage target hardware instruction set extensions.

R2023b: Conditional display of the Sample time parameter

The Discrete FIR Filter block no longer displays the Sample time parameter in the block parameters dialog box by default. The parameter is visible only if you set the sample time to a value other the default value (-1) at the command line or in an existing model. For more information, see Blocks for Which Sample Time Is Not Recommended.