Design Verifier™ supports design error detection, test generation, and property proving for
export-function models. The software creates a scheduler model that invokes the
export-function models, and then performs the analysis on the scheduler model. The
scheduler model invokes the function calls based on the sample times and priorities set
in the top model. By default, the software saves the scheduler model in
You can analyze export-function models with periodic and aperiodic function-call groups.
If the model consists of aperiodic function-call or global Simulink Function call, the scheduler has an additional port called the
FcnTriggerPort. For more information, see Export-Function Models Overview.
These topics cover examples that explain a periodic function-call subsystem and global Simulink Function that you can use as an AUTOSAR server runnable.
Simulink Design Verifier does not support:
Models that include export functions with multiple function-call initiators.
Masked model blocks that export Simulink Function blocks.
Scoped Simulink functions in export-function models.