Transmit and Receive Tone Using IP Core Generation Workflow on RFSoC Device

This example uses:

This example shows how to design and implement a hardware algorithm, which transmits and receives a tone signal, on RFSoC device by using the IP core geneartion workflow. This example also shows how to use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. The RFSoC device has built-in features that enforce the time alignment for samples from multiple channels across different tiles. While channels within a single tile are aligned in time, there is no guarantee of alignment with channels from different tiles. You can enable MTS to correct this issue. By enabling MTS, the RF Data Converter measures latency across different tiles and then applies sample delays to ensure that samples align correctly.

In this example, you generate HDL code for the algorithm as an IP core and integrate it in a reference design to build a system. Then, you deploy the system to hardware and visualize the received signal in Simulink®.

This example supports these hardware platforms:

Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit and XM500 balun card

Xilinx Zynq UltraScale+ RFSoC ZCU208 evaluation kit and XM655 balun card

Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit and XM655 balun card

Introduction

Using the IP core generation workflow, you can focus on the algorithm component and integrate it in a predefined reference design that defines the architecture. This workflow can be a good option for rapid prototyping when a reference design that meets your system requirements is available for deployment.

For modeling an algorithm with architecture, such as by using external memory and input/output (I/O) in Simulink, use the SoC Blockset™ product. For an example that shows how to model the algorithm and FPGA or SoC architecture and that shows the workflow to design and implement the complete SoC model, see Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design.

This example contains two models. Both the models generate a sinusoid signal from the FPGA using the NCO block and send the signal through the digital-to-analog converter (DAC) channels of the RFSoC device. Then the signal is received back from the analog-to-digital converter (ADC) channels in the FPGA. The receive-side FPGA has the logic to capture data in memory. Then the received data from memory is visualized in Simulink using the host I/O models. These two models differ slightly from one another.

For Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, use the following models.

soc_real_datacapture_zcu111 — Capture real data with one channel in the internal BRAM FIFO.

soc_IQ_MTS_datacapture_zcu111 — Capture complex in-phase/quadrature (I/Q) data with two channels in the internal BRAM FIFO and MTS enabled.

For Xilinx Zynq UltraScale+ RFSoC ZCU208 evaluation kit, use the following models.

soc_real_datacapture_zcu208

soc_IQ_MTS_datacapture_zcu208

For Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit, use the following models.

soc_real_datacapture_zcu216

soc_IQ_MTS_datacapture_zcu216

Simulate Model with Real Data Interface

In the model soc_real_datacapture_zcu111, the DUT sends and receives real data to and from the RF Data Converter. Simulate the model and observe the frequency spectrum of the DAC output for the transmitted tone signal of 108 MHz at a sample rate of 2048 MSPS. Also, observe the frequency spectrum of the ADC captured data for the received tone signal of 108 MHz at a sample rate of 512 MHz after decimation. Modify the numerically-controlled oscillator (NCO) tone frequency value by changing the value in the block NCO Freq (MHz), and then observe the corresponding change in the tone signal on the spectrum analyzer.

open_system('soc_real_datacapture_zcu111')

close_system('soc_real_datacapture_zcu111')

Simulate Model with Complex Data Interface and MTS

In the model soc_IQ_MTS_datacapture_zcu111, the DUT sends and receives complex data to and from the RF Data Converter. This model also shows how the MTS works on the hardware board by using two ADC channels from different tiles. As the RF Data Converter block does not model the latencies of DAC and ADC channels, the outputs of all ADC channels are always in sync with each other. Simulate the model and observe the frequency spectrum of the outputs from both the two DAC channels and the two ADC channels.

When using MTS, use ADC and DAC channels that are connected to the differential SMA ports on the XM500. The single-ended baluns introduce amplitude and phase offsets between channels, even when MTS is enabled.

open_system('soc_IQ_MTS_datacapture_zcu111')

close_system('soc_IQ_MTS_datacapture_zcu111')

Implementation

Hardware Setup for ZCU111 Kit for soc_real_datacapture_zcu111

Connect the SMA connectors on the XM500 balun card to complete the loopback between the DACs and ADCs, according to the connections provided in the following table.

Hardware Setup for ZCU111 Kit for soc_IQ_MTS_datacapture_zcu111

Connect the SMA connectors on the XM500 balun card to complete the loopback between the DACs and ADCs, according to the connections provided in the following table.

To implement the model on a supported SoC board, use the HDL Coder™ IP core generation workflow. To add the HDL Code tab to the Simulink toolstrip, open the Apps gallery and select HDL Coder.

In the Configuration Parameters dialog box of the model, set the HDL workflow, target platform, and reference design by following these steps.

1. In the left pane, expand HDL Code Generation and then select Target.

2. Set Workflow to IP Core Generation.

3. Set Target Platform to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit. Ensure that the Synthesis Tool is set to Xilinx Vivado.

4. Ensure that the Reference Design parameter is set to Generic design with real DAC/ADC and real-time interfaces for soc_real_datacapture_zcu111 and to Generic design with I/Q DAC/ADC and real-time interfaces for soc_IQ_MTS_datacapture_zcu111.

5. Ensure that the AXI4 stream to software data width parameter under Reference Design Settings is set to 64 for soc_real_datacapture_zcu111 and to 128 for soc_IQ_MTS_datacapture_zcu111.

6. As the model has RF Data Converter block, all the parameter values provided in RF Data Converter block are considered for code generation. If model has no block, then reference design parameters are considered for code generation.

To automatically map the interface of the IP, follow these steps.

1. Identify the IP core subsystem for code generation by selecting the Transmit and Receive Tone subsystem.

2. On the System on Chip tab, click Map Interfaces.

To view and edit the generated IP core interface mapping, follow these steps.

1. On the HDL Code toolstrip tab, click Target Interface.

2. In the IP Core panel, on the Interface Mapping tab, click the refresh button to load the mapping.

3. Edit the mapping until you map each DUT port and the mapping table appears as shown below.

4. Click the check button to validate the mapping.

Generate the HDL IP core and the FPGA bitstream files by following these steps.

1. On the HDL Code tab, click Build Bitstream.

2. After the HDL IP core generation finishes, an external shell opens for FPGA synthesis. Wait for the synthesis to complete. The FPGA synthesis often takes more than 30 minutes to complete.

For more information about the IP core generation workflow, see Get Started with IP Core Generation from Simulink Model (HDL Coder).

Run on Hardware

Program the FPGA on the SoC board by following these steps.

1. To download the bitstream, in the Simulink Toolstrip, on the HDL Code tab, select Build Bitstream > Program Target Device.

2. Verify your generated IP core on the hardware by using the generated host model. This model contains Simulink blocks that connect your hardware and interact with your IP core. To generate a host interface model, on the Simulink Toolstrip, on the HDL Code tab, select Build Bitstream > Software Interface Model.

3. After downloading the bitstream, run the soc_real_datacapture_hostiio_interface model (modified version of the generated host interface model) for soc_real_datacapture and soc_IQ_MTS_datacapture_hostiio_interface model for soc_IQ_MTS_datacapture_zcu111 to get the data back to the host from the hardware.

Below is the plot showing the alignement of data received from two ADC channels from different tiles for soc_IQ_MTS_datacapture_zcu111.

Implement and Run on ZCU208 and ZCU216

To generate the IP core and run the models soc_real_datacapture_zcu208, soc_real_datacapture_zcu216, soc_IQ_MTS_datacapture_zcu208, and soc_IQ_MTS_datacapture_zcu216 on the hardware, follow the steps in the previous sections of this example and use the hardware setup as described in this section for connections.

Connect the SMA connectors on the XM655 balun card to complete the loopback between the DACs and ADCs, according to the connections provided in the following tables.

Hardware Setup for ZCU208 and ZCU216 Kits for model with real data interface

Hardware Setup for ZCU208 and ZCU216 Kits for model with complex (IQ) data interface

Conclusion

Using the IP core generation workflow, you implemented an algorithm that transmitted a tone signal and received it back into the FPGA on the RFSoC device. You verified that the system worked as expected on the hardware. You can use this example as a reference and prototype for your wireless algorithm on the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, Xilinx Zynq UltraScale+ RFSoC ZCU208 evaluation kit, or Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit.