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CCSDS RS Encoder

Encode message into RS codeword according to CCSDS standard

  • Library:
  • Wireless HDL Toolbox / Error Detection and Correction

  • CCSDS RS Encoder block

Description

The CCSDS RS Encoder block encodes message symbols into a Reed-Solomon (RS) codeword according to the Consultative Committee for Space Data Systems (CCSDS) standard [1]. The block accepts message symbols and a samplecontrol bus and outputs encoded codeword data, a samplecontrol bus, and a nextFrame signal that indicates when the block is ready to accept new input message symbols.

The block also supports shortened message lengths. You can use this block in a CCSDS transmitter for satellite communication. The block provides an architecture suitable for HDL code generation and hardware deployment.

Ports

Input

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Input message symbols, specified as an integer in the range 0 to 255. Every integer represents a symbol.

The number of input message symbols per frame must be equal to p × I, where p can be any integer in the range from 1 to k. k is the message length and I is the interleaving depth specified on the block mask.

To provide proper outputs, the block requires a minimum frame gap of (255 – k) × I clock cycles between the input frames.

double and single data types are allowed for simulation, but not for HDL code generation. For HDL code generation, specify this value in fixdt(0,8,0) or uint8 format.

Data Types: double | single | uint8 | fixdt(0,8,0)

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the input frame

  • end — Indicates the end of the input frame

  • valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

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Encoded codeword symbols, returned as an integer in the range 0 to 255. The output data type is the same as the input data type.

The block outputs N + (255 – k) × I number of codeword symbols per frame, where N is the number of input message symbols. k is the message length specified using the Message length (k) parameter and I is the interleaving depth specified using the Interleaving depth (I) parameter.

Data Types: double | single | uint8 | fixdt(0,8,0)

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the output frame

  • end — Indicates the end of the output frame

  • valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Parameters

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Select the message length.

Select the interleaving depth.

Algorithms

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To form an RS codeword, the CCSDS RS Encoder block generates parity symbols and appends them to the input message symbols. RS code is a cyclic code, so the input message symbols are considered message polynomial coefficients and the code generator a generator polynomial. The generator polynomial divides the message polynomial to obtain a remainder polynomial that represents parity symbols. This figure shows the implementation of the block when you set the Message length (k) parameter to 239 and the Interleaving depth (I) parameter to 1. The encoding circuit in the figure shows the polynomial division logic.

CCSDS RS Encoder architecture

In this figure, g0, g1, g2 g3, and so on up to gn – 1 represent the generator polynomial coefficients and D0, D1, D2, D3, and so on up to Dn – 1 represent registers, where n is equal to 255 – k and k is the Message length (k) parameter value specified on the block mask. The registers store the parity symbols.

The GF multiplier used in the circuit stores all possible GF multiplication outputs for the encoder. These GF multipliers are implemented on the hardware as LUTs. These LUTs consume more hardware resources, so an efficient bit-serial multiplication algorithm [3] is used for the GF multiplier logic. This algorithm leverages the dual-basis representation and makes use of the field trace concept of the Galois field to compute the product. In this process, the values in the registers are updated for every input message symbol. When the last input message symbol of the current frame arrives, the values in the registers are considered parity symbols for the frame.

Similarly, if the Interleaving depth (I) parameter is set to 3, three sets of registers are required for each codeword to store the parity symbols. The number of GF adders and multipliers remains the same, 16, which is equal to 255 – k. For each input message symbol, the consecutive register sets Set 1, Set 2, or Set 3 are used in the parity computation. When the last input message symbol of the current frame arrives, the parity symbols are deinterleaved from each set to form an output parity sequence as shown in this figure.

CCSDS RS Encoder architecture

References

[1] TM Synchronization and Channel Coding. Recommendation for Space Data System Standards. CCSDS 131.0-B-3. Blue Book. Issue 3. Washington, D.C.: CCSDS, September 2017.

[2] TM Synchronization and Channel Coding. Summary of Concept and Rationale CCSDS 130.1-G-3. Green Book. Issue 3, June 2020.

[3] Hsu, In-Shek , et al. "The VLSI Implementation of a Reed— Solomon Encoder Using Berlekamp’s Bit-Serial Multiplier Algorithm." IEEE Transactions on Computers, vol. C–33, no. 10 (October 1984): 906–11. https://doi.org/10.1109/TC.1984.1676351.

Extended Capabilities

Version History

Introduced in R2022a

See Also

Blocks

Functions