Design, analyze, and deploy hardware/software applications for Xilinx and Intel SoC devices
Have questions? Contact sales.
Have questions? Contact sales.
SoC Blockset™ enables you to simulate and analyze the performance of algorithms on programmable SoCs and ASICs. You can deploy these algorithms as hardware and software applications for prototyping and production.
The blockset lets you build models of hardware architectures by defining interfaces between processor cores, programmable logic, memory, and peripherals. You can use the models to partition algorithms between programmable logic and processors to analyze the tradeoffs between hardware and software implementation. The blockset also lets you specify task scheduling of software applications.
The SoC Builder app automates deployment by building IP cores and software for Arm® cores and programming development boards from Simulink® (with HDL Coder™ and Embedded Coder®).
SoC Blockset supports the analysis of deployed applications in hardware with performance diagnostics and software profiling tools. Supported devices include Xilinx® Zynq®-7000 SoCs, Zynq Ultrascale+ MPSoCs/RFSoCs, and Versal™ ACAPs, as well as Intel® SoC FPGAs.
Perform preliminary analysis of your design to determine whether the software tasks in your application can be scheduled on your chosen hardware. Start with a functional architecture of the application in System Composer™ and allocate functional components to processors or programmable logic.
Analyze system designs using predefined models of the latest Xilinx programmable SoC devices, then use the SoC Builder tool to deploy to development boards for testing.
Documentation (Versal, RFSoC/MPSoC)
Examples (Versal, RFSoC/MPSoC)
With Wireless HDL Toolbox™, simulate and deploy a 5G NR MIB recovery algorithm or a 5G NR SIB1 recovery algorithm for FR1 and FR2 using an SoC Blockset implementation targeted to Xilinx Zynq UltraScale+ RFSoC boards.
Analyze Simulink models or MATLAB® algorithms to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures for FPGA, ASIC, and SoC devices, evaluate design tradeoffs, and explore hardware/software partitioning options.
Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.
Model task execution of embedded software as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration. Model software interrupts generated by FPGA fabric. Apply statistics to simulate nondeterministic task durations or incorporate task durations measured during hardware testing.
Generate HDL Coder reference designs directly from SoC Blockset models, then use the HDL Workflow Advisor tool to integrate IP cores created with HDL Coder.
Use the OS Customizer tool to modify and add libraries to the Linux® distribution for your embedded processor. Customize the embedded Linux operating system of supported boards.
Evaluate vision, communications, and radar applications while taking into account the effects of processor, FPGA, and DDR memory subsystems. Implement motor and power electronics controllers partitioned between processors and programmable logic.
Examples (vision, communications, radar, motor control)