Reducing Risk with Model-Based Design: Q&A with Philips Healthcare

“Design changes that took us a week to hand-code in VHDL and test on hardware can be simulated and verified in 30 minutes with Model-Based Design.”


Develop a novel digital RF power subsystem for use in MRI systems


Use Simulink to model, simulate, and verify the design, and use HDL Coder to generate consistent and predictable VHDL code for the FPGA implementation


  • Design issues resolved early in development
  • Tradeoffs rapidly assessed and implemented
  • Process consistency and predictability improved

With headquarters in the Netherlands and more than 37,000 employees in 100 countries, Philips Healthcare is a leader in cardiac care, acute care, and home healthcare.

What led you to look for a new way of working?

We were developing a digital RF power system for a magnetic resonance imaging (MRI) system, and we needed precise control over system timing and linearity. In the past, we would write an initial version of our algorithm in C and then translate it into VHDL for implementation on an FPGA—a process that was slow and error-prone.

Why Model-Based Design?

Model-Based Design speeds up design iterations by making it easier for our engineers to debug algorithms, evaluate algorithm ideas, and assess design tradeoffs. After modeling the components in our RF transmission chain in Simulink®, we run bit-true simulations to debug and optimize the design. We generate VHDL® from the model for implementation on an FPGA, eliminating the errors introduced during translation of algorithms from C to VHDL.

What results have you seen so far?

We’ve reduced risk with Model-Based Design by identifying and resolving problems earlier in development and by generating consistent HDL code. Model-Based Design enables us to rapidly evaluate design tradeoffs. For example, when we saw that the 24-stage FIR filter in our initial design would consume too many FPGA resources, we modeled and verified a simpler filter in Simulink. Instead of spending days handwriting VHDL, we completed this design change in less than an hour.