Verilog Testbench

What Is a Verilog Testbench?

A conventional Verilog® testbench is a code module that describes the stimulus to a logic design and checks whether the design’s outputs match its specification. Many engineers use MATLAB® and Simulink® to create system testbenches for specification models because the software provides a productive and compact notation to describe algorithms, as well as visualization tools for examining algorithm behavior. They then develop Verilog testbenches based on the system testbenches.

MATLAB or Simulink users have several options for verifying that HDL algorithm realizations are correct without manually coding Verilog testbenches.

Using HDL Cosimulation as an Alternative to Verilog Testbenches

Instead of writing a Verilog testbench, you can use a MATLAB or Simulink testbench in combination with an HDL simulator to verify your design under test (DUT). HDL Verifier™ automates this cosimulation process. The MATLAB or Simulink testbench compares output values from the HDL simulator with expected values from a truth model and reports “miscompares.”

Two diagrams displaying the processes of conventional testbench generation and automatic testbench generation using MATLAB and Simulink.

Automatic testbench generation accelerates the creation of new FPGA and ASIC verification environments.​

Using FPGA-in-the-Loop Testing as an Alternative to Verilog Testbenches

You can also use a MATLAB or Simulink testbench with a DUT that has been programmed into an AMD®Intel®, or Microchip® FPGA development board through FPGA-in-the-loop simulation. You can use HDL Verifier with FPGA vendor tools to compile the HDL, build a programming file, load the file onto the development board, and enable communication between the MATLAB or Simulink session and the board. With FPGA-in-the-loop, there is no need to generate a Verilog testbench because MATLAB or Simulink serves this purpose.

Using SystemVerilog DPI Testbench Generation as an Alternative to Verilog Testbenches

Another alternative to using a Verilog testbench is based on exporting code to HDL simulators. SystemVerilog, an extension of Verilog used for testbench development, is supported by all popular HDL simulators. With the SystemVerilog Direct Programming Interface (DPI), you can integrate C/C++ code with simulators such as Synopsys® VCS®, Cadence® Xcelium™, and Siemens® ModelSim® or Questa®. Using HDL Verifier in combination with MATLAB Coder™ or Simulink Coder™, you can generate SystemVerilog DPI testbenches to verify products.

To access DPI Generation for MATLAB code or Simulink subsystems, first download and install the add-on ASIC Testbench for HDL Verifier.

HDL Verifier can generate SystemVerilog DPI testbenches in two different forms:

  • Component testbench: If you generate a C component from a Simulink subsystem for use as a DPI component, you can generate a SystemVerilog testbench. The testbench verifies the generated DPI component against data vectors from your Simulink model. (See Generate SystemVerilog DPI Component.)
  • HDL code testbench: If you generate HDL code from a Simulink subsystem using HDL Coder™, you can generate a SystemVerilog testbench. This testbench compares the output of the HDL implementation against the results of the Simulink model. (See Verify HDL Design Using SystemVerilog DPI Testbench.)

Using UVM Component or Environment Generation as an Alternative to Verilog Testbenches

Universal Verification Methodology (UVM) enables a standardized form of design verification used in FPGA and ASIC design projects. The main goal of UVM verification is to improve design verification efficiency through the use of reusable verification components. With ASIC Testbench, you can generate UVM test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways:

  • Generate a UVM top model with a testbench and a behavioral DUT. Use the generated UVM top module as a test environment and replace the generated behavioral DUT with your own simulation model.
  • Generate UVM test components and integrate them into your existing UVM environment.

When you use HDL Coder to generate HDL, you can generate a Verilog testbench for a subsystem. HDL Coder generates a Verilog testbench by running a Simulink simulation to capture input vectors and expected output data for your DUT. HDL Coder writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files (.dat).

During HDL simulation, the HDL testbench reads the saved stimulus from the .dat files. The testbench compares the actual DUT output with the expected output.

See also: MATLAB for FPGA, ASIC, and SoC development, HDL Coder, HDL Verifier, Vision HDL Toolbox, MATLAB Coder, Simulink Coder, ASIC Testbench for HDL Verifier