Prototype Deep Learning Networks on FPGA
R2026bDeep Learning HDL Toolbox™ provides classes to create objects to deploy series deep learning networks to target FPGA and SoC boards. Before deploying deep learning networks onto target FPGA and SoC boards, leverage the methods to estimate the performance and resource utilization of the custom deep learning network. After you deploy the deep learning network, use MATLAB to retrieve the network prediction results from the target FPGA board.
Classes
Functions
Topics
- Prototype Deep Learning Networks on FPGA and SoC Devices
Accelerate the prototyping, deployment, design verification, and iteration of your custom deep learning network running on a fixed bitstream by using the
dlhdl.Workflowobject. - Profile Inference Run
Obtain performance parameters of an inference run performed for a pretrained series network and a specified target FPGA board.
- Multiple Frame Support
Improve the performance of your deployed deep learning network by using the multiple frame support feature.
Featured Examples
Logo Recognition Network
Create, compile, and deploy a dlhdl.Workflow object that has Logo Recognition Network as the network object using the AMD SoC Blockset Support Package for AMD FPGA and SoC Devices. Use MATLAB® to retrieve the prediction results from the target device.
Deploy Transfer Learning Network for Lane Detection
Create, compile, and deploy a lane detection convolutional neural network (CNN) to an FPGA, and use MATLAB® to retrieve the prediction results.
Image Category Classification by Using Deep Learning
Create, compile, and deploy a dlhdl.Workflow object with ResNet-18 as the network object by using the AMD SoC Blockset Support Package for AMD FPGA and SoC Devices. Use MATLAB® to retrieve the prediction results from the target device. ResNet-18 is a pretrained convolutional neural network that has been trained on over a million images and can classify images into 1000 object categories (such as keyboard, coffee, mug, pencil, and many animals). You can also use VGG-19 and DarkNet-19 as the network objects.
Image Classification Using Neural Network on FPGA
Train, compile, and deploy a dlhdl.Workflow object that has ResNet-18 neural network to an FPGA and use MATLAB® to retrieve the prediction results.
Defect Detection
Deploy a custom trained series network to detect defects in objects such as hexagon nuts. The custom networks were trained by using transfer learning. Transfer learning is commonly used in deep learning applications. You can take a pretrained network and use it as a starting point to learn a new task. Fine-tuning a network with transfer learning is usually much faster and easier than training a network with randomly initialized weights from scratch. You can quickly transfer learned features to a new task using a smaller number of training signals. This example uses two trained series networks, trainedDefNet.mat and trainedBlemDetNet.mat.
Bicyclist and Pedestrian Classification by Using FPGA
Deploy a custom trained network to detect pedestrians and bicyclists based on their micro-Doppler signatures. This network is taken from the Pedestrian and Bicyclist Classification Using Deep Learning example from the Phased Array Toolbox. For more details on network training and input data, see Pedestrian and Bicyclist Classification Using Deep Learning.
Visualize Activations of a Deep Learning Network by Using LogoNet
Feed an image to a convolutional neural network and display the activations of the different layers of the network. Examine the activations and discover which features the network learns by comparing areas of activation to the original image. Channels in earlier layers learn simple features like color and edges, while channels in the deeper layers learn complex features. Identifying features in this way can help you understand what the network has learned.
Running Convolution-Only Networks by Using FPGA Deployment
Typical classification networks include a sequence of convolution layers followed by one or more fully connected layers. Recent research results indicate that better performance is achieved for feature extraction and recognition by using the convolution layer activations directly, instead of those from the subsequent fully connected layers.
Vehicle Detection Using ResNet-18 Based YOLO v2 Deployed to FPGA
Train and deploy a you only look once (YOLO) v2 object detector.
Classify ECG Signals Using DAG Network Deployed to FPGA
Classify human electrocardiogram (ECG) signals by deploying a transfer learning trained SqueezeNet network trainedSN to a Xilinx® Zynq® Ultrascale+™ ZCU102 board.
Speech Command Recognition by Using FPGA
Deploy a custom pretrained dlnetwork that detects the presence of speech commands in audio to a Xilinx™ Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit. This example uses the pretrained network that was trained by using the Speech Commands Dataset [1]. To create the pretrained network, see Speech Command Recognition Using Deep Learning.
Modulation Classification by Using FPGA
Deploy a pretrained convolutional neural network (CNN) for modulation classification to the Xilinx™ Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit. The pretrained network is trained by using generated synthetic, channel-impaired waveforms.
Human Pose Estimation by Using Segmentation DAG Network Deployed to FPGA
Create, compile, and deploy a dlhdl.Workflow object by using the AMD SoC Blockset Support Package for AMD FPGA and SoC Devices. The Workflow object has a custom trained human pose estimation network as the network object. The network detects and outputs poses of people present in an input image of size 256-by-192. To train the network, see Estimate Body Pose Using Deep Learning.
Detect Objects Using YOLO v3 Network Deployed to FPGA
Deploy a trained you only look once (YOLO) v3 object detector to a target FPGA board. You then use MATLAB® to retrieve the object classification from the FPGA board.
Deploy Semantic Segmentation Network Using Dilated Convolutions on FPGA
Deploy a trained semantic segmentation network that uses dilated convolutions to a Xilinx® Zynq® Ultrascale+™ ZCU102 SoC development kit. Semantic segmentation networks like DeepLab [1] make extensive use of dilated convolutions, also known as atrous convolutions because they can increase the receptive field of the layer without increasing the number of parameters or computations.
Increase Image Resolution Using VDSR Network Running on FPGA
Create a high-resolution image from a low-resolution image using a very-deep super-resolution (VDSR) neural network running on an FPGA. Use Deep Learning HDL Toolbox™ to deploy the VDSR network and MATLAB® to retrieve the high-resolution image. To create the trained VDSR network used in this example, see Increase Image Resolution Using Deep Learning.
Detect Objects Using YOLOv4-tiny Network Deployed to FPGA
Perform object detection using a YOLO v4 tiny network deployed to an FPGA.
CSI Feedback with Autoencoders Implemented on an FPGA
Demonstrates how to use an autoencoder neural network to compress downlink channel state information (CSI) over a clustered delay line (CDL) channel. CSI feedback is in the form of a raw channel estimate array. In this example, the autoencoder network is implemented on an FPGA using the Deep Learning HDL Toolbox™.
Detect Objects Using YOLOX-Tiny Network Deployed to FPGA
Deploy a trained You Only Look Once X-tiny object detector (YOLOX-Tiny) to a target FPGA board.
