deploy
Class: dlhdl.Workflow
Package: dlhdl
Deploy the specified neural network to the target FPGA board
Syntax
Description
deploy(
programs the specified
target board with the bitstream and deploys the deep learning network on it.workflowObject
)
Input Arguments
workflowObject
— Workflow
dlhdl.Workflow
object
Workflow, specified as a dlhdl.Workflow
object.
Examples
Deploy LogoNet to Intel Arria 10 SoC Development Kit
Deploy VGG-19 to the Intel®
Arria® 10 SoC development kit that has single
data types.
The deploy
function starts programming the FPGA device, displays
progress messages, and the time it takes to deploy the network.
snet = vgg19; hTarget = dlhdl.Target('Intel'); hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'arria10soc_single','Target',hTarget); hW.deploy
### Programming FPGA bitstream using JTAG ... ### Programming FPGA bitstream has completed successfully. tableOut = offset_name offset_address allocated_space _______________________ ______________ _________________ "InputDataOffset" "0x00000000" "24.0 MB" "OutputResultOffset" "0x01800000" "4.0 MB" "SystemBufferOffset" "0x01c00000" "52.0 MB" "InstructionDataOffset" "0x05000000" "20.0 MB" "ConvWeightDataOffset" "0x06400000" "276.0 MB" "FCWeightDataOffset" "0x17800000" "472.0 MB" "EndOffset" "0x35000000" "Total: 848.0 MB" ### Loading weights to FC Processor. ### 4% finished, current time is 14-Jun-2020 18:31:07. ### 8% finished, current time is 14-Jun-2020 18:31:32. ### 12% finished, current time is 14-Jun-2020 18:31:58. ### 16% finished, current time is 14-Jun-2020 18:32:23. ### 20% finished, current time is 14-Jun-2020 18:32:48. ### 24% finished, current time is 14-Jun-2020 18:33:13. ### 28% finished, current time is 14-Jun-2020 18:33:39. ### 32% finished, current time is 14-Jun-2020 18:34:04. ### 36% finished, current time is 14-Jun-2020 18:34:30. ### 40% finished, current time is 14-Jun-2020 18:34:56. ### 44% finished, current time is 14-Jun-2020 18:35:21. ### 48% finished, current time is 14-Jun-2020 18:35:46. ### 52% finished, current time is 14-Jun-2020 18:36:11. ### 56% finished, current time is 14-Jun-2020 18:36:36. ### 60% finished, current time is 14-Jun-2020 18:37:02. ### 64% finished, current time is 14-Jun-2020 18:37:27. ### 68% finished, current time is 14-Jun-2020 18:37:52. ### 72% finished, current time is 14-Jun-2020 18:38:17. ### 76% finished, current time is 14-Jun-2020 18:38:43. ### 80% finished, current time is 14-Jun-2020 18:39:08. ### 84% finished, current time is 14-Jun-2020 18:39:33. ### 88% finished, current time is 14-Jun-2020 18:39:58. ### 92% finished, current time is 14-Jun-2020 18:40:23. ### 96% finished, current time is 14-Jun-2020 18:40:48. ### FC Weights loaded. Current time is 14-Jun-2020 18:41:06
Deploy Quantized LogoNet to Xilinx ZCU102 Development Kit
Create a file in your current working directory called
getLogoNetwork.m
. Enter these lines into the file:function net = getLogoNetwork data = getLogoData; net = data.convnet; end function data = getLogoData if ~isfile('LogoNet.mat') url = 'https://www.mathworks.com/supportfiles/gpucoder/cnn_models/logo_detection/LogoNet.mat'; websave('LogoNet.mat',url); end data = load('LogoNet.mat'); end
Create an image datastore and split 70 percent of the images into a training data set and 30 percent of the images into a validation data set.
curDir = pwd; newDir = fullfile(matlabroot,'examples','deeplearning_shared','data','logos_dataset.zip'); copyfile(newDir,curDir); unzip('logos_dataset.zip'); imds = imageDatastore('logos_dataset', ... 'IncludeSubfolders',true, ... 'LabelSource','foldernames'); [imdsTrain,imdsValidation] = splitEachLabel(imds,0.7,'randomized');
Create a
dlhdl.Workflow
object which has quantized LogoNet as the network argument,zcu102_int8
as the bitstream, andhTarget
as the target argument.To quantize the network, you need the products listed under
FPGA
in Quantization Workflow Prerequisites.% Save the pretrained SeriesNetwork object snet = getLogoNetwork; % Create a Target object and define the interface to the target board hTarget = dlhdl.Target('Xilinx','Interface','Ethernet'); % Create a Quantized Network Object dlquantObj = dlquantizer(snet,'ExecutionEnvironment','FPGA'); dlquantObj.calibrate(imdsTrain); % Create a workflow object for the SeriesNetwork and using the FPFA bitstream hW = dlhdl.Workflow('Network', dlquantObj, 'Bitstream', 'zcu102_int8','Target',hTarget);
Deploy the
dlhdl.Workflow
object to your target FPGA board by using thedeploy
method.% Deploy the workflow object hW.deploy;
When you call the
deploy
method, the method returns:### Programming FPGA Bitstream using Ethernet... Downloading target FPGA device configuration over Ethernet to SD card ... # Copied /tmp/hdlcoder_rd to /mnt/hdlcoder_rd # Copying Bitstream hdlcoder_system.bit to /mnt/hdlcoder_rd # Set Bitstream to hdlcoder_rd/hdlcoder_system.bit # Copying Devicetree devicetree_dlhdl.dtb to /mnt/hdlcoder_rd # Set Devicetree to hdlcoder_rd/devicetree_dlhdl.dtb # Set up boot for Reference Design: 'AXI-Stream DDR Memory Access : 3-AXIM' Downloading target FPGA device configuration over Ethernet to SD card done. The system will now reboot for persistent changes to take effect. System is rebooting . . . . . . ### Programming the FPGA bitstream has been completed successfully. offset_name offset_address allocated_space _______________________ ______________ _________________ "InputDataOffset" "0x00000000" "48.0 MB" "OutputResultOffset" "0x03000000" "4.0 MB" "SystemBufferOffset" "0x03400000" "60.0 MB" "InstructionDataOffset" "0x07000000" "8.0 MB" "ConvWeightDataOffset" "0x07800000" "8.0 MB" "FCWeightDataOffset" "0x08000000" "12.0 MB" "EndOffset" "0x08c00000" "Total: 140.0 MB" ### Loading weights to FC Processor. ### FC Weights loaded. Current time is 12-Jun-2020 13:17:56
Version History
Introduced in R2020b
See Also
compile
| getBuildInfo
| predict
| dlquantizer
| dlquantizationOptions
| calibrate
| validate
| predictAndUpdateState
| resetState
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