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AXI4-Interface Read

Read data from IP core on Xilinx Zynq Platform

Add-On Required: This feature requires the Embedded Coder Support Package for Xilinx Zynq Platform add-on.


This block reads a data vector from a contiguous group of memory-mapped registers on an HDL Coder™ generated IP core. The AXI4-Interface Read block, using the central interconnect of the processing system, provides simple memory-mapped communication with the IP core on the FPGA. This block is best suited for low-throughput communication, such as inspecting status, state, or control registers.

The data flows from the HDL Coder IP Core through a central interconnect on its path to the AXI4-Interface Read block.

  • AXI4-Interface Read block



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The N-by-1 vector read from memory-mapped registers on the IP core, starting from the Register offset.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean


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Enter the path and name of the IP core.


If you use HDL Coder to generate the IP core, HDL Coder maps the IP core to /dev/mwipcore.

Enter the offset of the register from the base address of the IP core. The block reads data from this register. Use the hex2dec function when you specify the address offset using a hexadecimal number character vector.


If you use HDL Coder to generate the IP core, you can get the value of the address offset from the “Register Address Mapping” section of the Custom IP Core Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).

Enter the size of the data vector to be read from the IP core device.

Select the data type used by the IP core.

The signal data output by the AXI4-Interface Read block polls directly from the IP core using AXI4-Lite protocol. The Sample time parameter value or the base-rate of the subsystem specifies the polling rate of the registers.

Version History

Introduced in R2013a