AXI4-Stream IIO Write
Write AXI4-Stream Data using IIO
Add-On Required: This feature requires the Embedded Coder Support Package for Xilinx Zynq Platform add-on.
Embedded Coder Support Package for Xilinx Zynq Platform
This block writes data to the direct-memory-access (DMA) buffer of the specified AXI4-Stream IP core device by using the Industrial I/O (IIO) library drivers. The AXI4-Stream IIO Write block enables low-latency, high-throughput data transmission from your model on the processor to the IP core on the FPGA. This diagram shows the control signals and path of the data after leaving this block.
Data — Data frame to DMA buffer
This port outputs the N-by-1 vector written to memory in the DMA buffer transfer. This port is unnamed until the Valid port is enabled.
Valid — Status of stream write to IP core
This port outputs a validation flag indicating a successful write of the data to
the IP core, where
1 indicates a successful write.
To enable this port, set Data timeout (seconds) to a finite value.
IIO device name — File name of IP core device
mwipcore0:mm2s0 (default) | character array
Enter the name and channel of the IP core on the FPGA as a colon separated list. If
you are using HDL Coder™ to generate the IP core, HDL Coder maps the IP core to
mwipcore0 and uses channel
mm2s0. For more information on getting IIO device names and
channels, see Tips.
Data timeout (seconds) — Timeout for DMA stream read
Inf (default) | positive scalar
Specify the maximum time out delay for the DMA stream write.
To get a list of available IIO device names and channels, open a terminal into the Xilinx® Zynq® hardware board, and execute this command.
Introduced in R2018b