Delay Balancing

To achieve more efficient hardware usage and higher clock rates in your model, HDL Coder™ has several optimizations, block implementations, and options that introduce discrete delays into your model. Optimizations such as output pipelining, streaming, or resource sharing can introduce delays. Some block implementations, such as the Newton-Raphson and CORDIC architecture, inherently introduce delays in the generated code.

When optimizations or block implementation options introduce delays along the critical path in a model, the numerical calculations of the original model and generated model or HDL code can differ from each other because equivalent delays are not introduced on other, parallel signal paths. Manual insertion of compensating delays along other paths is possible, but is prone to error and does not scale well to large models that have many signal paths or multiple sample rates.

To avoid this issue, HDL Coder provides delay balancing. HDL Coder detects introduction of new delays along one path, and then inserts matching delays on the other paths.

Specify Delay Balancing

You can set delay balancing for the ports in your device under test (DUT) subsystem. You can disable delay balancing for specific parts of your design by using the HDL block property BalanceDelays for input and output ports. See Delay Balancing Considerations.

Disable Delay Balancing for Constant Sources

A stable path is a path where the initial source to the path is constant. If your model contains a stable path outside the DUT and connects to the top-level DUT subsystem and you want to reduce the amount of resources needed, you can disable delay balancing for the stable path by disabling the HDL block property BalanceDelays on the DUT-level Inport block. The BalanceDelays property affects only DUT-level Inport blocks. For example, in this model, you can disable BalanceDelays for the DUT_Subsystem's Inport block, which is also input port h_in1, because the input to the Inport block is a Constant block.

DUT subsystem with a constant input coming into the DUT through an Inport block

To disable the HDL block property BalanceDelays for an Inport block using the HDL Block Properties dialog box:

Right-click the Inport block.
Select HDL Code > HDL Block Properties.
Set BalanceDelays to off.

To disable delay balancing for an Inport block from the command line, use the hdlset_param function.

If your DUT includes a subsystem hierarchy and you disable BalanceDelays on the DUT-level Inport block, the delay balancing on the stable path does not occur within the lower-level hierarchy if the stable path extends to that lower-level hierarchy. For an example, see Control the Scope of Delay Balancing.

Note

When you disable BalanceDelays on DUT-level Inport blocks for stable paths and distributed pipelining is enabled for the model, change the Pipeline distribution priority configuration parameter from Numerical Integrity to Performance if you see delays inserted on stable paths in the generated model. For more information, see Pipeline distribution priority.

To disable the HDL block property BalanceDelays for an Outport block using the HDL Block Properties dialog box:

Right-click the Outport block.
Select HDL Code > HDL Block Properties.
Set BalanceDelays to off.

To disable delay balancing for an Outport block from the command line, use the hdlset_param function.

If your model contains a stable path that originates in the DUT, meaning that there is a Constant block as an input in the DUT, and a parallel path to the stable path has latency introduced from optimizations, delay balancing does not insert a matching delay on the stable path that contains the Constant block because the output value of the block is a constant. Not inserting the delay results in less resources needed for the design, but also results in an initial simulation mismatch. To resolve the simulation mismatch, add matching delays to the Constant block path by setting the HDL block property OutputPipeline to the number of matching delays needed at the output of the Constant block.

Delay Balancing Considerations

When you generate HDL code, delay balancing is an essential part of code optimizations. If any optimizations are enabled, you must balance pipelines introduced as a part of those optimizations. Failure to balance automatically inserted pipeline delays causes issues in generated code deployed in hardware.

For multirate models, HDL Coder might generate a large number of pipeline registers that can prevent the HDL design from fitting onto an FPGA. Before you disable delay balancing for the model, see Delay Balancing on Multirate Designs and Optimize Generated HDL Code for Multirate Designs with Large Rate Differentials.

Resolving Delay Balancing Errors in a Feedback Loop Design

When you enable delay balancing on a model and that model contains a feedback loop in the DUT subsystem, during HDL code generation, you may see this error:

An extra 10 cycles of latency introduced by optimizations in the feedback loop cannot be offset using design delays for the loop latency budget. If you are modeling at data rate (high-level description of algorithm without hardware implementation details), refer to the clock-rate pipelining report for more details. If you are modeling at clock rate, consider increasing the latency budget by adding more design delays in the feedback loop. Refer to the delay balancing report for more details. Offending block: <modelname>/Subsystem/Add1. The error message includes links to the clock-rate pipelining report and delay balancing report.

In this situation, the error is a result of pipelining in feedback loops that introduces latency and breaks the functional equivalence between the original and generated model. However, disabling delay balancing for the entire model results in a simulation mismatch between your original model and the generated model. To resolve this issue, either:

Use clock-rate pipelining. See the Use Clock-Rate Pipelining section in Resolve Simulation Mismatch When Pipelining with a Feedback Loop Outside the DUT.
Increase the latency budget by adding more design delays. See the Model with Latency in a Feedback Loop section in Use Delay Absorption While Modeling with Latency.

Delay Absorption During Delay Balancing

The delay balancing optimization applies delay absorption to your model, which uses design delays in place of pipeline delays introduced from optimizations to prevent unused latency from being added in your design. Similar to other pipeline optimizations, such as distributed pipelining, delay absorption moves existing delays to the point where an optimization introduces latency. Delay absorption allows you to model with latency, which means that you can add design delays in the original design to simulate the extra delays introduced by optimizations in the generated design. If there are enough design delays, the extra delays introduced by optimizations are absorbed and no additional cycles of latency are reported at the DUT output ports. Modeling with latency prevents timing differences between the original model and generated model and allows HDL Coder to generate a functionally equivalent model to the generated HDL code. Modeling with latency at the clock rate is useful for high-frequency, high-throughput applications, such as signal processing and wireless system design. For more information, see Use Delay Absorption While Modeling with Latency.

For delay absorption to run during HDL code generation:

Place a Delay block with a delay length equal to or greater than the block latency after the block that introduces latency. You can place the Delay block anywhere downstream on the data path from the block that introduces latency. For example, if you have a series of floating-point operators that accumulate to create a large amount of latency, you can place a single Delay block with a delay length equal to the total latency from the operators at the end of the series of operators.
For delay absorption to take place inside of a triggered subsystem, enable the model parameter Use trigger signal as clock.

For more information on floating-point operations and delay absorption, see Latency Considerations with Native Floating Point.

Delay Balancing Report

When you generate code for a design under test (DUT) HDL Coder produces the optimization report. Select the Delay Balancing section of the report. The DUT can be a subsystem, model, or model reference.

The Delay Balancing Report shows latency changes, pipeline and phase delay at the output ports, delay absorption information, and the number of pipelines added at the output ports to match the delays. If delay balancing fails, the report displays the criteria that was violated and the link to any block or subsystem that caused delay balancing to fail.

Delay Balancing Limitations

Subsystem-Level Restrictions

HDL Coder does not support delay balancing if:

A subsystem with BlackBox architecture has the ImplementationLatency block property set to a negative value.
To fix this error, for ImplementationLatency, enter a nonnegative integer.

Sample Time Restrictions

HDL Coder does not support delay balancing if you introduce latency from optimizations and:

The sample time is continuous.
Your design has an infinite sample time output.