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Optimization Basics

Hierarchy flattening, delay balancing, validation model, constrained overclocking, and feedback loop highlighting

Optimize your design for a target FPGA or SoC device by applying optimizations such as hierarchy flattening, delay balancing, or feedback loop highlighting. Applying base optimizations helps to generate more hardware-efficient HDL code and properly simulate the generated code.



Resolve Numeric Mismatch with Delay Balancing

Learn how to resolve numerical mismatch issues after HDL code generation.