Phase-Locked Loops

Design and simulate analog phase-locked loop (PLL) systems

Design a PLL system starting from basic foundation blocks or from a family of reference architectures. Simulate and analyze the PLL system to verify key performance metrics until you meet the system specifications.

You can start by providing the specifications and impairments of each foundation block and connect the blocks to model different PLL architectural models (bottom-up approach). Alternatively, you can start from complete system-level models of typical PLL architectures and customize those models to meet your system specifications (top-down approach).

Use Measurements and Testbenches throughout the design process to verify the specifications of the blocks and of the entire system in presence of imperfections.

Blocks

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Building Blocks

Charge Pump	Output a current proportional to the difference in duty cycle between two input ports
Loop Filter	Model second-, third-, or fourth-order passive loop filter
PFD	Phase/frequency detector that compares phase and frequency between two signals
VCO	Model voltage controlled oscillator
Ring Oscillator VCO	Model ring oscillator VCO (Since R2021a)
Single Modulus Prescaler	Integer clock divider that divides frequency of input signal
Dual Modulus Prescaler	Integer clock divider with two divider ratios
Fractional Clock Divider with Accumulator	Clock divider that divides frequency of input signal by fractional number
Fractional Clock Divider with DSM	Delta Sigma Modulator based fractional clock divider

Reference Architectures

Fractional N PLL with Accumulator	Frequency synthesizer with accumulator based fractional N PLL architecture
Fractional N PLL with Delta Sigma Modulator	Frequency synthesizer with delta sigma modulator based fractional N PLL architecture
Integer N PLL with Dual Modulus Prescaler	Frequency synthesizer with dual modulus prescaler based integer N PLL architecture
Integer N PLL with Single Modulus Prescaler	Frequency synthesizer with single modulus prescaler based integer N PLL architecture

Topics

Phase Noise in Oscillators
Learn how to obtain reliable phase noise data from an oscillator data sheet.

Featured Examples

PLL Design and Verification Using Data Sheet Specifications

Use Mixed-Signal Blockset™ to model a commercial off-the-shelf integer-N phase-locked loop (PLL) with dual modulus prescaler operating around 4 GHz. You can verify the PLL performance, including phase noise.

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50x PLL Frequency Synthesizer Behavior Study and Measurements

Different measurements and scopes available to study the behavior of a PLL (phase-locked loop). In this example, the 1 MHz reference frequency of the PLL is multiplied by an integer (50).This drives to VCO output to 50 MHz.

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PLL With Dual Modulus Prescaler

How a PLL (phased locked loop) model works with a dual modulus prescaler frequency divider.

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Phase Noise at PLL Output

Predict the phase noise at the output of a phase-locked loop (PLL), simulate the PLL using the PLL Testbench, and compare the simulation results to theoretical predictions.

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Circuit Design Details Affect PLL Performance

Use the Linear Circuit Wizard block to evaluate the effect of loop filter circuit design details on the performance of a phase-locked loop.

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Tune Phase-Locked Loop Using Loop-Shaping Design

Tune the components of a passive loop filter to improve the loop bandwidth of a phase-locked loop system.

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Digital Phase Locked Loop

Model a digital phase locked loop using the Mixed-Signal Blockset™. In a digital phase locked loop, phase detection is performed by a time to digital converter (TDC), loop filtering is performed by a digital filter, and the oscillator is a digitally controlled oscillator (DCO). This example demonstrates a behavioral model of a TDC, using the BiquadFilter from the DSP System Toolbox™ as the digital loop filter, and using VCOs and DACs from the Mixed-Signal Blockset to model the DCO.

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Model PLLs in the Phase Domain

Model a phase-locked loop (PLL) in the phase domain, compare the analytic results to simulation results in the time domain, and identify the advantages and disadvantages of each approach. Most PLL analysis is performed in the phase domain, and this example shows you how to produce a complete analysis using minimal time and efforts.

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