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Data Converters

Simulate successive-approximation-register (SAR) and flash analog to digital data converters (ADC)

Simulate and analyze performance metrics of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.

Blocks

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Sampling Clock SourceGenerate clock signal with aperture jitter
Flash ADCN-bit ADC with flash architecture
SAR ADCN-bit successive approximation register (SAR) based ADC
Binary Weighted DACN-bit DAC based on R-2R weighted resistor architecture
Segmented DACConvert large digital input to analog signal using arrangement of smaller DACs

Topics

Compare SAR ADC to Ideal ADC

This example shows a comparison of the SAR ADC from the Mixed-Signal Blockset™ to the ideal ADC model with impairments presented in Analyzing Simple ADC with Impairments.

Effect of Metastability Impairment in Flash ADC

This example shows how to customize a flash Analog to Digital Converter (ADC) by adding the metastability probability as an impairment.

Compare Binary Weighted DAC to Ideal DAC

This example shows a comparison of the Binary Weighted DAC from the Mixed-Signal Blockset™ to an ideal DAC model.

Featured Examples