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Post-Layout Verification Workflow

Using the post-layout verification process, you can verify the system-level signal integrity and timing margins for your fully or partially routed PCB design databases. The process supports single-board and multi-board analysis, along with connectivity through packages, connectors and cabling.

The post-layout verification flow is the same for each PCB database type. First you need to import the PCB databases. If there are multiple boards in the system, connect the instances. Then run assignment and setup the transfer net and simulation properties. Then run simulations and analyze the results.

Setup Board

To import PCB database and setup boards, open the Post-Layout Setup and Assignment dialog box by clicking the Setup and Assignment... button in the verification tab of the Serial Link Designer or Parallel Link Designer app. The are three major sections using which you can setup a board:

  • Boards — The PCB database that you import in the app. To vary the PCB database with different stackups, voltages, or models, create multiple boards with different names.

  • Instances — Internal copy of the board. To use the same board more than once, create an instance for each use.

  • Connections — Pin-to-pin path from the pins of a reference designator on one instance to the pins of a reference designator on a second instance.

To start the board import and setup process, click the Import and Setup Board button in the Post-Layout Setup and Assignment dialog box. This opens the Import and Setup Board dialog box. You can define the PCB database type and files, view and edit the stackups, view and set the voltage nets, and manage the part models. You can also modify the setup for, copy or delete a selected board.

If the PCB database has been revised, you can update the internal PCB database by reimporting the board. When re-importing the board, you can choose to overwrite the default stackup, voltage assignments, and parts assignments. You must rerun assignment after re-importing boards.

Run Assignment

To automatically associate the nets in the PCB database with the transfer nets, you need to run assignment. This allows you to set up all the nets in an interface for simulation in a fraction of the time it would take to set up each net in the interface individually.

On the PCB, the pins that are directly connected by the copper are represented by a CAD net. A CAD net may only be one part of the net that will be simulated. For example, it may be the connection from a driver to a one pin of a series termination resistor.

An extended net is one or more CAD nets that are connected by series devices, such as resistors and connectors. The app combines the CAD nets into extended nets as part of the assignment process. It then groups the extended nets together based on the IBIS buffer models on the pins. The PENETs are then matched to transfer nets in the interface.

During the assignment process, the Serial Link Designer or Parallel Link Designer app looks at the pins on the components of type IC and Connector for IBIS buffer models. The app uses the IBIS file and component specified in the part number to match pin numbers in the PCB database with the model name in the IBIS file. It then groups the extended nets together in the pin equivalent nets (PENETs). Finally, the PENETs are compared to the transfer nets on the interface.

If a transfer net has the same number of pins with the same models as a PENET, all extended nets in that PENET are assigned to the transfer net. If the app does not find a match for the PENET, it creates a system transfer net (STNET). If an extended net does not have enough pins with models to simulate,it is assigned to a system unsimulatable net(SUNET).

When running assignment, you can control the granularity of the pin equivalence in two ways:

  • Assign by name — Two equivalent pins have same part and IBIS buffer model.

  • Assign by type — Two equivalent pins have same part and IBIS buffer model type. This is less restrictive than assigning by model name, and will result in fewer PENETs.

To start the assignment process, click the Assignment Setup... button in the Post-Layout Setup and Assignment dialog box. Once you are satisfied with the setup, click the Run Assignment button.

Setup Transfer Nets

If the interface you are working in has pre-layout schematics, post-layout verification process uses the transfer nets from the reference schematic set. This re-uses the transfer net properties and reduces or eliminates the need to set up transfer nets in post-layout.

If there are no existing transfer nets in the interface, the app creates sheets with system transfer nets (STNETs). You can rename them and set them up for simulation. To edit the transfer net properties, click the TNET Properties button in the Post-Layout Verification tab.

For more information, see Transfer Nets in Serial Link Designer and Transfer Nets in Parallel Link Designer.

Setup Simulation

Before you run simulation, set up the stimulus pattern for each designator on a transfer net. You can also modify some SPICE options. For more information, see Stimulus Patterns in Serial Link Design and Stimulus Patterns in Parallel Link Design.

Next, select the nets for post-layout verification and add them to the list of nets to simulate. Use the Include and Exclude buttons in the Extended Net Simulation panel in the Post-Layout Verification tab to modify the list of nets to simulate.

You can set the simulation control options in the Post-Layout Simulation Control panel in the Post-Layout Verification tab. The global controls affect all extended nets selected for simulation:

  • Corners — Select IC and etch process corners.

  • State — Select the simulation state.

  • AC Noise — Select the AC noise parameter source.

You can overrider the global control for corner settings by selecting the Use for Corners option for an associated reference schematic sheet.

Run Simulation

Simulate the selected nets by selecting Run > Simulate. This launches the Post-Layout SI/Timing simulation dialog box.

You can define how the app creates, run, and monitors the simulations in the Process Controls section. Define the simulations steps to be performed in the SI/Timing Simulation Steps section. The Simulation Summary section shows the status of the simulation steps as they are run. There app also generates log and report files at each step that you can use to determine the source of the problem.