Bit Set

Set specified bit of stored integer to one

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Libraries:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Bit Set block sets the specified bit of the stored integer to one. Scaling is ignored.

You can specify the bit to be set to one with the Index of bit parameter, where bit zero is the least significant bit.

Examples

Using a Bit Set block

If the Bit Set block is turned on for bit 2 is set to 1.

A vector of constants 2.^[0 1 2 3 4] is represented in binary as [00001 00010 00100 01000 10000].

With bit 2 set to 1, the result is [00101 00110 00100 01100 10100], which is represented in decimal as [5 6 4 12 20].

Ports

Input

Port_1 — Input signal

scalar | vector

Input signal with the specified bit of the stored integer.

Data Types: single | double | Boolean | fixed point

Output

Port_1 — Output signal

scalar | vector

Output signal with the specified bit set to 1.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

Index of bit — Index of bit

0 (default) | scalar | vector

Index of bit where bit 0 is the least significant bit.

Programmatic Use

Block Parameter: iBit

Type: character vector

Values: positive integer

Default: '0'

Block Characteristics

Data Types	Booleana | fixed point | integer
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	no
Zero-Crossing Detection	no
a Bit operations are not recommended for use with Boolean signals.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a