Bus Creator

Create bus from input signals

• Library:

• Simulink / Commonly Used Blocks

  Simulink / Signal Routing

  HDL Coder / Signal Routing

Description

The Bus Creator block combines a set of input signals into a bus. You can connect any signal types to the input ports, including other buses. You can access signals in a bus by using a Bus Selector block.

Elements of a bus must have unique names. If duplicate names are present, the Bus Creator block appends the port number to all input signal names. For signals that do not have names, the Bus Creator block generates names in the form signaln, where n is the port number connected to the signal. You can refer to signals by name when you search for their sources or select signals for connection to other blocks. For signal naming guidelines, see Signal Names and Labels.

Tip

For models that include buses composed of many elements, consider using the In Bus Element and Out Bus Element blocks. You can use these bus element port blocks instead of Inport with Bus Selector blocks for inputs, and Outport with Bus Creator blocks for outputs.

Bus element port blocks:

• Reduce signal line complexity and clutter in a block diagram.

• Make it easier to change the interface incrementally.

• Allow access to a bus element closer to the point of usage, avoiding the use of a Bus Selector and Goto block configuration.

Ports

Input

Port_1 — Accept signal to include in bus

real or complex values of any data type supported by Simulink^®

Input signals can have real or complex values of any data type supported by Simulink, including bus objects, arrays of buses, fixed-point, and enumerated data types. For details about data types, see Simulink, Data Types Supported by Simulink.

Output

Port_1 — Output bus signal

virtual or nonvirtual bus

Bus that combines the input signals.

Parameters

Number of inputs — Number of input ports

2 (default) | integer

Number of inputs, not fewer than two. Increasing the number of connected ports adds empty ports below the connected ports. Before you simulate the model, make sure that an input signal is connected to each input port.

When you modify the Number of inputs parameter, click Refresh to update the list of signals.

Tip

If all input ports are already connected, you can add an input port to the Bus Creator block by connecting another signal line to it. Interactively adding a port updates the Number of inputs parameter and adds the new signal to the list of signals in the bus.

Programmatic Use

Block Parameter: Inputs

Type: character vector

Values: integer greater than or equal to 2

Default: '2'

Signals in the bus — Input signals

list of signal names

List of input signals to combine into a bus. You can view all signals entering the block, including the signals contained in nested buses. An arrow next to a signal indicates that an input signal is a bus. To display the contents of that bus, click the arrow.

Signals in the bus are ordered from the top input port to the bottom input port. For a description of port order for various block orientations, see Port Location After Rotating or Flipping. To rearrange the signals in the output bus signal, use the Up and Down buttons. You can select multiple top-level contiguous signals in the Signals in the bus list to reorder or remove.

To find the source of any signal entering the block, select the signal in the Signals in the bus list and click the Find button. Simulink highlights the icon of the source, opening the subsystem that contains the signal source, if necessary.

Filter by name — Search term used to filter input signals

text

Search term used to filter a long list of input signals. Do not enclose the search term in quotation marks. The filter does a partial string search. To access filtering options, including using a regular expression to specify the search term, click the button to the right of the Filter by name edit box.

Enable regular expression — Option to filter using regular expressions

off (default) | on

Enable the use of MATLAB^® regular expressions for filtering signal names. For example, entering t$ in the Filter by name edit box displays all signals whose names end with a lowercase t (and their immediate parents). For details, see Regular Expressions (MATLAB).

Dependencies

To access this parameter, click the button to the right of the Filter by name edit box.

Show filtered results as a flat list — Option to display filtered results as a flat list

off (default) | on

Enable the flat list format that uses dot notation to reflect the hierarchy of bus signals based on the search text in the Filter by name edit box. By default, a tree list displays the filtered signals.

Dependencies

To access this parameter, click the button to the right of the Filter by name edit box

Output data type — Data type of output bus

'Inherit: auto' (default) | 'Bus: <object name>' | <data type expression>

Data type of the output bus.

If you select 'Bus: <object name>', specify a bus object. The bus object must be accessible when you update the diagram or simulate the model. To define a bus object using the Bus Editor, click the Show data type assistant button , then click the Edit button.

If you select '<data type expression>', specify an expression that evaluates to a data type. Do not specify a bus object as the expression.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: auto' | 'double' | 'single' | 'int8' | 'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'boolean' | 'fixdt(1,16,0)' | 'fixdt(1,16,2^0,0)' | 'Enum: <class name>' | 'Bus: <object name>'

Default: 'Inherit: auto'

Require input signal names to match signals above — Match input signal names to names listed in dialog box

off (default) | on

Optional check that input signal names match the signal names in the Bus Creator Block Parameters dialog box.

Tip

The Require input signal names to match signals above parameter might be removed in a future release. To enforce strong data typing, consider using the Override bus signal names from inputs parameter.

If you select Override bus signal names from inputs, Simulink software ignores the Require input signal names to match signals above setting.

If you change the Number of inputs programmatically, this parameter reverts to 'off'.

Rename selected signal — Name for currently selected signal

'' (default) | character vector

Name the currently selected input signal. See Signal Names and Labels for signal name guidelines.

Dependencies

To display this parameter, enable the Require input signal names to match signals above parameter.

Override bus signal names from inputs — Bus input signal name override

on (default) | off

By default, the Bus Creator block overrides bus signal names from inputs.

To inherit bus signal names from a bus object, clear this parameter. Clearing the parameter:

• Enforces strong data typing.

• Avoids having to enter a signal name multiple times: in the bus object and in the model. Entering the name multiple times can accidentally create signal name mismatches.

• Supports the array of buses requirement to have consistent signal names across array elements.

Alternatively, you can enforce strong data typing by checking that input signal names match the bus object element names.

• Keep the Override bus signal names from inputs check box selected.

• Set the Element name mismatch parameter to error.

Dependencies

To display this parameter, set the Output data type parameter to a bus object.

Programmatic Use

Block Parameter: InheritFromInputs

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Output as nonvirtual bus — Nonvirtual bus output

off (default) | on

Nonvirtual bus output from the Bus Creator block.

All signals in a nonvirtual bus must have the same sample time, even if the elements of the associated bus object specify inherited sample times for some elements. Any operation resulting in a nonvirtual bus containing signals with different sample rates generates an error. To change the sample time of a signal or bus that has a different sample time than the other nonvirtual bus input signals, use a Rate Transition block. For details, see Specify Bus Signal Sample Times.

To generate code that uses a C structure to define the structure of the bus output by this block, enable this parameter.

Dependencies

To display this parameter, set the Output data type parameter to a bus object.

Programmatic Use

Block Parameter: NonVirtualBus

Type: character vector

Values: 'on' | 'off'

Default: 'off'

Model Examples

Buses in Simulink

Introduces you to the following Simulink® bus signal capabilities: Bus Creator, Bus Selector, and Bus Assignment blocks

Open Model

Block Characteristics

Data Types	Boolean | bus | double | enumerated | fixed point | integer | single | string
Direct Feedthrough	no
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Bus Signals to Improve Readability of Model and Generate HDL Code (HDL Coder).

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion

Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.