NR CRC Encoder

Generate CRC code bits and append them to input data

Since R2021a

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Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The NR CRC Encoder block calculates and generates a short, fixed-length binary sequence, known as the cyclic redundancy check (CRC) checksum, appends it to each frame of streaming data samples, and outputs CRC-encoded data. The block accepts and returns a data sample stream with accompanying control signals. The control signals indicate the validity of the samples and the boundaries of the frame.

The block supports scalar and vector inputs and outputs data as either a scalar or vector based on the input data. To achieve higher throughput, the block accepts a binary vector or unsigned integer scalar input and implements a parallel architecture. The input data width must be less than or equal to the length of the CRC polynomial and the length of the CRC polynomial, must be divisible by the input data width. The block supports all CRC polynomials specified according to the 5G new radio (NR) standard 3GPP TS 38.212 [1]. When you select the CRC24C polynomial, the block supports dynamic CRC mask.

The block provides an interface and hardware-optimized architecture suitable for HDL code generation and hardware deployment.

Examples

NR CRC Encode and Decode Streaming Data

Use NR CRC Encoder and NR CRC Decoder blocks and compare their hardware-optimized results with results from 5G Toolbox™ functions.

• Open Script

Ports

Input

data — Input data

binary scalar | binary vector | unsigned integer scalar

Input data, specified as a binary scalar, binary vector, or unsigned integer scalar.

You can specify the input data with one of these options:

• Scalar – Specify an integer representing several bits. For this case, the block supports unsigned integer (uint8, uint16, or ufixN) and Boolean data types.

• Vector – Specify a vector of binary values of size N. For this case, the block supports Boolean and ufix1 data.

N is the input data width, and it must be less than or equal to the length of the CRC polynomial and a factor of the specified CRC polynomial length.

double and single data types are supported for simulation, but not for HDL code generation.

Example: For the CRC type CRC24A, the valid data widths are 24, 12, 8, 6, 4, 3, 2, and 1. An integer input is interpreted as a binary word. For example, when you specify a uint8 input of 19, it is equivalent to a vector input [0 0 0 1 0 0 1 1].

Data Types: double | single | ufix1 | uint8 | uint16 | Boolean | ufixN

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

CRCMask — CRC checksum mask

nonnegative integer

CRC checksum mask, specified as a nonnegative integer representing a binary word from 0 to 2^CRCLength – 1, where CRCLength is the length of the CRC polynomial.

This mask is typically a radio network temporary identifier (RNTI). The RNTI is used to XOR the CRC checksum.

Dependencies

To enable this port, set the CRC type parameter to CRC24C and select the Enable CRC mask input port parameter.

Data Types: ufix24

Output

data — CRC-encoded data

scalar | vector

CRC-encoded data with appended CRC checksum, returned as a scalar or vector. The output data type and size are the same as the input data.

Data Types: double | single | ufix1 | uint8 | uint16 | Boolean | ufixN

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Parameters

CRC type — Type of CRC

CRC16 (default) | CRC6 | CRC11 | CRC24A | CRC24B | CRC24C

Select the type of CRC. Each CRC type indicates a polynomial, as shown in this table.

CRC Type	Polynomial
CRC6	[1 1 0 0 0 0 1]
CRC11	[1 1 1 0 0 0 1 0 0 0 0 1]
CRC16	[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]
CRC24A	[1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1]
CRC24B	[1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1]
CRC24C	[1 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 1 1]

These CRC polynomials are specified according to the 5G NR standard 3GPP TS 38.212 [1].

Enable CRC mask input port — Enable CRC checksum mask input port

off (default) | on

Select this parameter to enable the CRCMask input port.

Dependencies

To enable this parameter, set the CRC type parameter to CRC24C.

Algorithms

When you use a binary vector or unsigned integer scalar input, the block implements a parallel CRC algorithm [2].

To provide high throughput for modern communications systems, the block implements the CRC algorithm with a parallel architecture. This architecture recursively calculates M bits of a CRC checksum for each W input bits. At the end of the frame, the final checksum result is appended to the message. For a polynomial length of M, the recursive checksum calculation for W bits in parallel is

$$X^{\text{'}}=F_W(\times )X(+)D.$$

F_W is an M-by-M matrix that selects elements of the current state for the polynomial calculation with the new input bits. D is an M-element vector that provides the new input bits, ordered in relation to the generator polynomial and padded with zeros. The block implements the (×) with logical AND and (+) with logical XOR.

Latency

The latency of the block varies with the CRC polynomial length, the type of input (scalar or vector), and the data width of the input. The latency of the block is calculated from the start of the input frame to the start of the output frame by using the formula (CRCLength/N) + 3 clock cycles, where N is the input data width.

The frame gap between two frames (that is, from ctrl.end of the first frame to ctrl.start of the next frame) must be greater than the length of the CRC polynomial plus the latency of the first frame. In case of continuous inputs, the block discards the first frame and starts processing the next frame.

Scalar Input

This figure shows a sample output and latency of the NR CRC Encoder block when you specify a scalar input of data type ufix8 with a data width of 8, and set the CRC type parameter to CRC16. The latency of the block is 5 clock cycles, as shown in this figure.

Vector Input

This figure shows a sample output and latency of the NR CRC Encoder block when you specify a vector input of data type ufix1 with a data width 3, set the CRC type parameter to CRC24C, and select the Enable CRC mask input port parameter. The latency of the block is 11 clock cycles, as shown in this figure.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the CRC polynomial length and the input data width.

This table shows the resource and performance data synthesis results of the block when the CRC type parameter is set to CRC24A for a scalar input of data type ufix1, scalar input of data type ufix24, and 24-by-1 vector input of data type ufix1. The generated HDL is targeted to the AMD^® Zynq^®- 7000 ZC706 evaluation board.

Input Data		Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
Scalar	ufix1	147	168	0	614.6
	ufix24	207	192	0	581.0
Vector		182	160	0	571.1

References

[1] 3GPP TS 38.212. “NR; Multiplexing and Channel Coding.” 3rd Generation Partnership Project; Technical Specification Group Radio Access Network.

[2] Campobello, G., G. Patane, and M. Russo. “Parallel CRC Realization.” IEEE Transactions on Computers 52, no. 10 (October 2003): 1312–19. https://doi.org/10.1109/TC.2003.1234528.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2021a