# NR CRC Encoder

Generate CRC code bits and append them to input data

• Library:
• Wireless HDL Toolbox / Error Detection and Correction

## Description

The NR CRC Encoder block calculates and generates a short, fixed-length binary sequence, known as the cyclic redundancy check (CRC) checksum, appends it to each frame of streaming data samples, and outputs CRC-encoded data. The block accepts and returns a data sample stream with accompanying control signals. The control signals indicate the validity of the samples and the boundaries of the frame.

The block supports scalar and vector inputs and outputs data as either a scalar or vector based on the input data. To achieve higher throughput, the block accepts a binary vector or unsigned integer scalar input and implements a parallel architecture. The input data width must be less than or equal to the length of the CRC polynomial and the length of the CRC polynomial, must be divisible by the input data width. The block supports all CRC polynomials specified according to the 5G new radio (NR) standard 3GPP TS 38.212 [1]. When you select the CRC24C polynomial, the block supports dynamic CRC mask.

The block provides an interface and hardware-optimized architecture suitable for HDL code generation and hardware deployment.

## Ports

### Input

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Input data, specified as a binary scalar, binary vector, or unsigned integer scalar.

You can specify the input data with one of these options:

• Scalar – Specify an integer representing several bits. For this case, the block supports unsigned integer (`uint8`, `uint16`, or `ufixN`) and `Boolean` data types.

• Vector – Specify a vector of binary values of size N. For this case, the block supports `Boolean` and `ufix1` data.

N is the input data width, and it must be less than or equal to the length of the CRC polynomial and a factor of the specified CRC polynomial length.

`double` and `single` data types are supported for simulation, but not for HDL code generation.

Example: For the CRC type `CRC24A`, the valid data widths are 24, 12, 8, 6, 4, 3, 2, and 1. An integer input is interpreted as a binary word. For example, when you specify a `uint8` input of `19`, it is equivalent to a vector input ```[0 0 0 1 0 0 1 1]```.

Data Types: `double` | `single` | `ufix1` | `uint8` | `uint16` | `Boolean` | `ufixN`

Control signals accompanying the sample stream, specified as a `samplecontrol` bus. The bus includes the `start`, `end`, and `valid` control signals, which indicate the boundaries of the frame and the validity of the samples.

• `start` — Indicates the start of the input frame

• `end` — Indicates the end of the input frame

• `valid` — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: `bus`

CRC checksum mask, specified as a nonnegative integer representing a binary word from 0 to 2CRCLength – 1, where CRCLength is the length of the CRC polynomial.

This mask is typically a radio network temporary identifier (RNTI). The RNTI is used to XOR the CRC checksum.

#### Dependencies

To enable this port, set the CRC type parameter to `CRC24C` and select the Enable CRC mask input port parameter.

Data Types: `ufix24`

### Output

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CRC-encoded data with appended CRC checksum, returned as a scalar or vector. The output data type and size are the same as the input data.

Data Types: `double` | `single` | `ufix1` | `uint8` | `uint16` | `Boolean` | `ufixN`

Control signals accompanying the sample stream, returned as a `samplecontrol` bus. The bus includes the `start`, `end`, and `valid` control signals, which indicate the boundaries of the frame and the validity of the samples.

• `start` — Indicates the start of the output frame

• `end` — Indicates the end of the output frame

• `valid` — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: `bus`

## Parameters

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Select the type of CRC. Each CRC type indicates a polynomial, as shown in this table.

CRC TypePolynomial
`CRC6`[1 1 0 0 0 0 1]
`CRC11`[1 1 1 0 0 0 1 0 0 0 0 1]
`CRC16`[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]
`CRC24A`[1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1]
`CRC24B`[1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1]
`CRC24C`[1 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 1 1]

These CRC polynomials are specified according to the 5G NR standard 3GPP TS 38.212 [1].

Select this parameter to enable the CRCMask input port.

#### Dependencies

To enable this parameter, set the CRC type parameter to `CRC24C`.

## Algorithms

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When you use a binary vector or unsigned integer scalar input, the block implements a parallel CRC algorithm [2].

To provide high throughput for modern communications systems, the block implements the CRC algorithm with a parallel architecture. This architecture recursively calculates M bits of a CRC checksum for each W input bits. At the end of the frame, the final checksum result is appended to the message. For a polynomial length of M, the recursive checksum calculation for W bits in parallel is

`${X}^{\text{'}}={F}_{W}\left(×\right)X\left(+\right)D.$`

FW is an M-by-M matrix that selects elements of the current state for the polynomial calculation with the new input bits. D is an M-element vector that provides the new input bits, ordered in relation to the generator polynomial and padded with zeros. The block implements the (×) with logical AND and (+) with logical XOR.

## References

[1] 3GPP TS 38.212. “NR; Multiplexing and Channel Coding.” 3rd Generation Partnership Project; Technical Specification Group Radio Access Network.

[2] Campobello, G., G. Patane, and M. Russo. “Parallel CRC Realization.” IEEE Transactions on Computers 52, no. 10 (October 2003): 1312–19. https://doi.org/10.1109/TC.2003.1234528.

## Version History

Introduced in R2021a